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1. 发明授权

US6146954A Minimizing transistor size in integrated circuits 失效
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US6146954A
公开(公告)日：2000-11-14
申请号：US119934
申请日：1998-07-21
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66545 , H01L21/2257 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在FET之前和之后制造FET和局部互连件的源极和漏极来形成多晶硅栅极和局部互连之间的最小绝缘空间形成FET的栅极。在形成栅极之前去除源极和漏极之间的绝缘层的一部分。优选地，在该方法中使用在绝缘层下方的半导体衬底上的蚀刻停止层。

2. 发明授权

US6051881A Forming local interconnects in integrated circuits 失效
标题翻译：在集成电路中形成局部互连
公开(公告)号：US6051881A
公开(公告)日：2000-04-18
申请号：US986097
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L23/522 , H01L23/535 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L28/20 , H01L21/7681 , H01L21/76895 , H01L27/0676
摘要： A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.
摘要翻译：一种方法和所得到的器件，通过在多晶硅栅极上形成绝缘层，并利用蚀刻阻挡层保护所选择的栅极和绝缘层，从而允许在多晶硅栅极之间形成最小的绝缘空间，从而局部互连金属化的开口可以不对准，并且所选择的门将被其蚀刻屏障保护，并且不暴露于开口。此外，局部互连导电材料可以通过栅极或不相关的电阻器，而不会使栅极/电阻器短路。

3. 发明授权

US5889697A Memory cell for storing at least three logic states 失效
标题翻译：用于存储至少三个逻辑状态的存储单元
公开(公告)号：US5889697A
公开(公告)日：1999-03-30
申请号：US947123
申请日：1997-10-08
申请人： Asim A. Selcuk , Craig S. Sander
发明人： Asim A. Selcuk , Craig S. Sander
IPC分类号： G11C11/56 , G11C11/00
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/3431 , G11C11/412
摘要： A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the pair of storage nodes. To store a third logic state, the third-level storage and refresh circuitry maintain the multi-level signals at both storage nodes at substantially equal intermediate levels.
摘要翻译：用于存储具有至少三个逻辑状态的数据的存储单元包括耦合到一对存储节点的一对存储设备和第三级存储和刷新电路。存储设备保持表示该对存储节点处的第一和第二逻辑状态的多电平信号。为了存储第三逻辑状态，第三级存储和刷新电路在两个存储节点处维持基本相等的中间级的多级信号。

4. 发明授权

US4884123A Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
标题翻译：使用阻挡衬里和回填导体材料的接触插头和互连
公开(公告)号：US4884123A
公开(公告)日：1989-11-28
申请号：US16429
申请日：1987-02-19
申请人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
发明人： Pankaj Dixit , Jack Sliwa , Richard K. Klein , Craig S. Sander , Mohammad Farnaam
IPC分类号： H01L29/43 , H01L21/28 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76877 , H01L21/76879 , Y10S257/915
摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry. The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon. The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

5. 发明授权

US4764800A Seal structure for an integrated circuit 失效
标题翻译：集成电路的密封结构
公开(公告)号：US4764800A
公开(公告)日：1988-08-16
申请号：US860597
申请日：1986-05-07
申请人： Craig S. Sander
发明人： Craig S. Sander
IPC分类号： H01L23/52 , H01L21/314 , H01L21/3205 , H01L23/525 , H01L27/04 , H01L23/48
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A seal structure for a semiconductor integrated circuit is disclosed. Contacts within and outside the region encircled by the seal structure are coupled by running a doped semiconductor region under the encircling seal. A reverse biased junction is formed at the interface of the seal and underlying doped semiconductor region. The best mode disclosed is related to sealing fuse components from the remainder of the circuit components while providing electrical coupling ability.
摘要翻译：公开了一种用于半导体集成电路的密封结构。由密封结构包围的区域内和外部的接触通过在环绕密封件下运行掺杂半导体区域来耦合。在密封件和下掺杂半导体区域的界面处形成反向偏置结。所公开的最佳模式涉及从电路部件的其余部分密封熔丝部件，同时提供电耦合能力。

6. 发明授权

US4714686A Method of forming contact plugs for planarized integrated circuits 失效
标题翻译：形成平面化集成电路的接触插塞的方法
公开(公告)号：US4714686A
公开(公告)日：1987-12-22
申请号：US761206
申请日：1985-07-31
申请人： Craig S. Sander , Balaji Swaminathan
发明人： Craig S. Sander , Balaji Swaminathan
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/283 , H01L21/308
CPC分类号： H01L21/28525 , H01L21/7684 , Y10S438/914 , Y10S438/945
摘要： A method for forming doped, conductive plugs to fill and planarize contact windows in integrated circuits is disclosed. The process is applicable to CMOS, NMOS and bipolar technologies. Discrete, sized, contact apertures formed superposing junction regions of a substrate are filled with semiconductor material and the semiconductor material is doped to match the conductivity type of the underlying junction regions. Thus, the integrated circuit structure is substantially planarized for formation of interconnect layers.
摘要翻译：公开了一种在集成电路中形成掺杂的导电插塞以填充和平坦化接触窗的方法。该工艺适用于CMOS，NMOS和双极技术。用半导体材料填充重叠的衬底的接合区域形成的分立尺寸的接触孔，并且掺杂半导体材料以匹配下面的结区域的导电类型。因此，集成电路结构基本上被平坦化以形成互连层。

7. 发明授权

US07026691B1 Minimizing transistor size in integrated circuits 有权
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US07026691B1
公开(公告)日：2006-04-11
申请号：US10042732
申请日：2001-04-25
申请人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Craig S. Sander , Rich K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christoper A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L31/113 , H01L31/119 , H01L23/48
CPC分类号： H01L29/78 , H01L21/2257 , H01L21/28123 , H01L21/76895 , H01L29/41775 , H01L29/41783 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在形成FET之前制造FET和局部互连的源极和漏极来形成栅极和局部互连之间的最小空间 FET的栅极。

8. 发明授权

US6046088A Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
标题翻译：使用场隔离自对准多晶硅栅极的方法及其结果
公开(公告)号：US6046088A
公开(公告)日：2000-04-04
申请号：US985400
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762
CPC分类号： H01L21/28123 , H01L21/76224 , H01L29/6659
摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.
摘要翻译：在诸如浅氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面多晶硅门在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

9. 发明授权

US4912540A Reduced area butting contact structure 失效
标题翻译：减少对接接触结构
公开(公告)号：US4912540A
公开(公告)日：1990-03-27
申请号：US230696
申请日：1988-08-05
申请人： Craig S. Sander , Richard K. Klein , Tat C. Choi
发明人： Craig S. Sander , Richard K. Klein , Tat C. Choi
IPC分类号： H01L21/768 , H01L29/04 , H01L23/48 , H01L29/34
CPC分类号： H01L21/76895 , H01L21/7684 , H01L21/76877
摘要： A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.
摘要翻译：提供了减小面积对接接触结构（10'），其特别适用于四晶体管静态RAM单元。形成了包括掺杂硅区域和位于其上方的一层或多层多晶硅和氧化物的结构，其中一层多晶硅可以是栅极多晶硅。然后通过所有上层进行各向异性蚀刻，所述上层包括可能存在的任何上多晶硅层，但在掺杂硅区域和存在的任何栅多晶硅层停止以形成接触孔（26'）。接触孔填充有诸如钨或多晶硅的材料的导电插塞（32）并被回蚀。在任一种情况下，与存在的所有多晶硅层和掺杂的硅区域接触。在各向异性蚀刻工艺中，采用两步蚀刻。第一蚀刻对于材料是非特异性的，以基本上相同的速率蚀刻所有相关材料（多晶硅和氧化物）并且继续通过任何上多晶硅层，但是在蚀刻掺杂硅区域或任何栅极多晶硅层之前终止 22）。第二蚀刻对于材料是特定的，比多晶硅或硅更快地蚀刻二氧化硅，因此停止在栅极多晶硅层和掺杂的硅区域。

10. 发明授权

US5844836A Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell 失效
标题翻译：具有通过局部互连到栅极电容器的电容增加的存储单元和用于制造这种单元的方法
公开(公告)号：US5844836A
公开(公告)日：1998-12-01
申请号：US822518
申请日：1997-03-24
申请人： Nicholas John Kepler , Asim A. Selcuk , Richard K. Klein , Craig S. Sander , John C. Holst , Christopher A. Spence , Raymond T. Lee , Stephen C. Horne
发明人： Nicholas John Kepler , Asim A. Selcuk , Richard K. Klein , Craig S. Sander , John C. Holst , Christopher A. Spence , Raymond T. Lee , Stephen C. Horne
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104
摘要： A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.
摘要翻译：在存储节点处具有增加的单元电容的静态随机存取存储器（SRAM）单元利用电容结构。电容结构包括多晶硅导电线与钨局部互连之间的电介质材料。多晶硅板各自连接到与SRAM单元相关联的横向晶体管的漏极。可以在局部互连和多晶硅导电线之间沉积诸如二氧化硅的电介质材料。电容器结构设置在与SRAM单元相关联的第一和第二N沟道下拉晶体管之间。

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