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1. 发明授权

US5524007A Network interface architecture for a packet switch communication system 失效
标题翻译：分组交换机通信系统的网络接口架构
公开(公告)号：US5524007A
公开(公告)日：1996-06-04
申请号：US165718
申请日：1993-12-13
申请人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , Lisa B. Johanson
发明人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , Lisa B. Johanson
IPC分类号： G06F13/42 , H04B1/16 , H04B1/38 , H04L12/56 , H04L12/64 , H04M1/73 , H04W92/02 , H04L12/40
CPC分类号： H04W92/02 , G06F13/423 , H04B1/1615 , H04B1/38 , H04J3/0697 , H04L12/56 , H04L12/64 , H04L12/6402 , H04W52/0245
摘要： An improved network interface architecture for a packet switch provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (NI) provides a mechanism (the NI-Bus) of passing all packets through the Network Interface or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The network interface architecture, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps. It also allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
摘要翻译：用于分组交换机的改进的网络接口架构使用公共分组结构在单个交换机中提供语音和数据的组合。它允许基于系统加载的带宽的动态分配。这不仅包括帧的语音或数据区域内的带宽，还包括语音和数据部分之间的带宽。网络接口（NI）提供了通过网络接口传递所有数据包或允许数据包设备在彼此之间直接传输数据包的机制（NI-Bus）。带宽分配可以容易地改变，因为控制和数据存储器彼此同步。根据本发明的网络接口架构允许数据分组和带宽分配的控制由单个交换设备控制。它同步数据的传输和总线带宽的分配。可以以非常高的比特率（例如40Mbps）来控制分组设备的控制。它还允许数据包设备直接传输数据包。它允许通过使用NI基本寄存器轻松重新分配带宽。

2. 发明授权

US5477541A Addressing technique for storing and referencing packet data 失效
标题翻译：用于存储和引用分组数据的寻址技术
公开(公告)号：US5477541A
公开(公告)日：1995-12-19
申请号：US165789
申请日：1993-12-13
申请人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , Hungkun J. Chang , Michael P. Nolan , John M. Kaczmarczyk , Lisa B. Johanson
发明人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , Hungkun J. Chang , Michael P. Nolan , John M. Kaczmarczyk , Lisa B. Johanson
IPC分类号： G06F13/42 , H04B1/16 , H04B1/38 , H04L12/56 , H04L12/64 , H04M1/73 , H04W92/02
CPC分类号： H04W92/02 , G06F13/423 , H04B1/1615 , H04B1/38 , H04L12/56 , H04L12/64 , H04L12/6402 , H04W52/0245
摘要： A hierarchical addressing technique is employed in a packet communications system to enhance flexibility in storing and referencing packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets received or to be transmitted.
摘要翻译：在分组通信系统中采用分层寻址技术来提高存储和参考分组信息的灵活性。该方法允许分组消息数据和某些分组控制数据存储在存储器位置中，而不必在传输分组之前在不同的存储器位置被复制。该方法优选地采用环形配置，其中一系列分组具有彼此顺序指向以形成接收或要发送的分组环的寻址机制。

3. 发明授权

US5517500A Packet handling method 失效
标题翻译：数据包处理方法
公开(公告)号：US5517500A
公开(公告)日：1996-05-14
申请号：US165784
申请日：1993-06-21
申请人： Richard E. White , Dale R. Buchhlz , Thomas A. Freeburg , Lisa B. Johanson
发明人： Richard E. White , Dale R. Buchhlz , Thomas A. Freeburg , Lisa B. Johanson
IPC分类号： G06F13/42 , H04B1/16 , H04B1/38 , H04L12/56 , H04L12/64 , H04M1/73 , H04W92/02 , H04L12/40
CPC分类号： H04W92/02 , G06F13/423 , H04B1/1615 , H04B1/38 , H04J3/0697 , H04L12/56 , H04L12/64 , H04L12/6402 , H04W52/0245
摘要： An improved network interface architecture for a packet switch provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (NI) provides a method (the NI-Bus) or passing all packets through the Network Interface or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The network interface architecture, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps. It also allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
摘要翻译：用于分组交换机的改进的网络接口架构使用公共分组结构在单个交换机中提供语音和数据的组合。它允许基于系统加载的带宽的动态分配。这不仅包括帧的语音或数据区域内的带宽，还包括语音和数据部分之间的带宽。网络接口（NI）提供了一种方法（NI-Bus）或通过网络接口传递所有数据包，或者允许数据包设备之间直接传输数据包。带宽分配可以容易地改变，因为控制和数据存储器彼此同步。根据本发明的网络接口架构允许数据分组和带宽分配的控制由单个交换设备控制。它同步数据的传输和总线带宽的分配。可以以非常高的比特率（例如40Mbps）来控制分组设备的控制。它还允许数据包设备直接传输数据包。它允许通过使用NI基本寄存器轻松重新分配带宽。

4. 发明授权

US5495482A Packet transmission system and method utilizing both a data bus and dedicated control lines 失效
标题翻译：分组传输系统和方法利用数据总线和专用控制线
公开(公告)号：US5495482A
公开(公告)日：1996-02-27
申请号：US719212
申请日：1991-06-21
申请人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , John M. Kaczmarczyk , Rita O'Brien
发明人： Richard E. White , Dale R. Buchholz , Thomas A. Freeburg , John M. Kaczmarczyk , Rita O'Brien
IPC分类号： G06F13/42 , H04B1/16 , H04B1/38 , H04L12/56 , H04L12/64 , H04M1/73 , H04W92/02 , H04L12/40
CPC分类号： H04W92/02 , G06F13/423 , H04B1/1615 , H04B1/38 , H04J3/0697 , H04L12/56 , H04L12/64 , H04L12/6402 , H04W52/0245
摘要： A common communication controller is linked to a plurality of peripheral devices by a network interface bus. Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller and peripherals.
摘要翻译：公共通信控制器通过网络接口总线链接到多个外围设备。包含信息的包通过总线通过总线传送，该总线由并行包总线和用于实现通信协议的多个控制线组成，该通信协议通过利用附加的直接命令行来提高分组通信的效率通信控制器和外设。

5. 发明授权

US5138327A Antenna pattern selection for optimized communications and avoidance of people 失效
标题翻译：天线模式选择优化通信和避免人员
公开(公告)号：US5138327A
公开(公告)日：1992-08-11
申请号：US641373
申请日：1991-01-15
申请人： Hungkun J. Chang , William K. Doss , Michael P. Nolan , Dale R. Buchholz , Thomas A. Freeburg , John McKown , Richard E. White
发明人： Hungkun J. Chang , William K. Doss , Michael P. Nolan , Dale R. Buchholz , Thomas A. Freeburg , John McKown , Richard E. White
IPC分类号： H04B7/08 , H04L12/56 , H04W16/24 , H04W36/00 , H04W36/30 , H04W40/02
CPC分类号： H04B7/088 , H04W16/24 , H04W40/02
摘要： An antenna selection technique is used in an RF communincation system in which user modules (UM) communicate with at least one node. The UM's and nodes each have multiple antennae. The combination of each UM and node antenna is evaluated at the UM. Based on at least signal quality, the UM selects its antenna and the best node antenna for use. An alternate antenna is selected if a person is determined to be present in a predetermined area adjacent a UM corresponding to a predetermined RF power level.
摘要翻译：在RF通信系统中使用天线选择技术，其中用户模块（UM）与至少一个节点通信。 UM和节点各有多个天线。在UM处评估每个UM和节点天线的组合。基于至少信号质量，UM选择其天线和最佳节点天线使用。如果人被确定存在于与预定的RF功率电平相对应的UM附近的预定区域中，则选择备用天线。

6. 发明授权

US5440545A Packet delivery system 失效
标题翻译：分组传送系统
公开(公告)号：US5440545A
公开(公告)日：1995-08-08
申请号：US100403
申请日：1993-08-02
申请人： Dale R. Buchholz , William K. Doss , R. Lee Hamilton, Jr. , Richard E. White , Karen Robbins
发明人： Dale R. Buchholz , William K. Doss , R. Lee Hamilton, Jr. , Richard E. White , Karen Robbins
IPC分类号： H04L1/12 , H04L1/16 , H04L1/18 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L47/34 , H04L1/1614 , H04L1/1809 , H04L29/06 , H04L1/1854 , H04L69/324
摘要： A packet switching system (100) having a packet switch (140) employs an acknowledgement scheme in order assure the delivery of all fragments (310) comprising a fragmented data packet (300) to improve overall system throughput during the handling of packets (310) that require reassembly. When packet fragments (310) are lost, corrupted or otherwise unintelligible to a receiving device (92, 94), the acknowledgement scheme permits retransmission of the missing data. In addition, a second acknowledgment signal is scheduled by system processing resources (110) in order to verify the successful delivery of all retransmitted data.
摘要翻译：具有分组交换机（140）的分组交换系统（100）采用确认方案，以便确保包括分段数据分组（300）的所有分段（310）的传递，以在处理分组（310）期间改善总体系统吞吐量需要重新组装。当分组片段（310）丢失，损坏或以其它方式对于接收设备（92,94）不了解时，确认方案允许丢失数据的重传。另外，由系统处理资源（110）调度第二确认信号，以验证所有重发数据的成功传送。

7. 发明授权

US5475681A Wireless in-building telecommunications system for voice and data communications 失效
标题翻译：用于语音和数据通信的无线建筑内电信系统
公开(公告)号：US5475681A
公开(公告)日：1995-12-12
申请号：US166194
申请日：1994-01-31
申请人： Richard E. White , Thomas A. Freeburg , James J. Berken , Roy T. Ogasawara , James E. Mitzlaff , Gregory J. Bedlek
发明人： Richard E. White , Thomas A. Freeburg , James J. Berken , Roy T. Ogasawara , James E. Mitzlaff , Gregory J. Bedlek
IPC分类号： G06F13/42 , H04B1/16 , H04B1/38 , H04L12/56 , H04L12/64 , H04M1/73 , H04W92/02 , H04B7/15 , H04L12/403
CPC分类号： H04W92/02 , G06F13/423 , H04B1/1615 , H04B1/38 , H04L12/56 , H04L12/64 , H04L12/6402 , H04W52/0245
摘要： An improved network interface architecture for a packet switch provides a mechanism for handling voice and data packets. Bandwidth allocation can be changed because control and data memories are synchronized to one another. A hierarchical addressing technique is employed to enhance flexibility in handling packet information. This method permits packet message data and certain packet control data to be stored in memory locations without having to be duplicated at a different memory location prior to transmission of the packet. In an exemplary wireless TDMA packet network a control module (CM) sends a time stamp relative to the beginning of its frame in a synchronization packet allowing each of a plurality of user modules (UM) to maintain synchronization relative to the CM. The CM uses a plurality of directional antennas and transmits the synchronization packets over each antenna over a predetermined number of frames. The UMs use a receive time stamp to identify the beginning of a received synchronization packet. The difference between the time stamps combined with a delay constant is used by the UMs to adjust time synchronization to the CM frame. Packets are communicated between the controller and the peripherals at the UM and CM over a bus using a communication protocol which increases the efficiencies of packet communications by allowing additional direct command lines between the communications controller and peripherals.
摘要翻译：用于分组交换机的改进的网络接口架构提供了用于处理语音和数据分组的机制。可以改变带宽分配，因为控制和数据存储器彼此同步。采用分层寻址技术来提高处理分组信息的灵活性。该方法允许分组消息数据和某些分组控制数据存储在存储器位置中，而不必在传输分组之前在不同的存储器位置被复制。在示例性无线TDMA分组网络中，控制模块（CM）在同步分组中相对于其帧的开始发送时间戳，允许多个用户模块（UM）中的每一个相对于CM保持同步。 CM使用多个定向天线，并在预定数量的帧上通过每个天线发送同步分组。 UM使用接收时间戳来识别接收到的同步分组的开始。时间戳与延迟常数之间的差异由UM用于调整与CM帧的时间同步。通过使用通信协议的通信协议，在UM和CM之间的控制器和外设之间通过总线传送数据包，通过允许通信控制器和外围设备之间的附加直接命令行来提高数据包通信的效率。

8. 发明授权

US5396490A Packet reassembly method and apparatus 失效
标题翻译：分组重组方法和装置
公开(公告)号：US5396490A
公开(公告)日：1995-03-07
申请号：US856276
申请日：1992-03-23
申请人： Richard E. White , McGrath James D. , Dale R. Buchholz
发明人： Richard E. White , McGrath James D. , Dale R. Buchholz
IPC分类号： H04Q7/38 , H04L12/56 , H04L12/66 , H04L29/06 , H04L29/08 , H04Q7/22 , H04Q7/24 , H04Q7/26 , H04Q7/30 , H04Q11/04
CPC分类号： H04L12/56 , H04L12/66 , H04L29/06 , H04L69/324
摘要： A packet switching system (100) employs packet reassembly hardware (214) in a packet switch (140) to improve overall system throughput during the handling of transmission packets (310) that require reassembly. In this manner, reassembly is accomplished with minimal processor (110) intervention and without having to duplicate the message data portion (312) of a transmission packet (310) into a different memory location prior to retransmission.
摘要翻译：分组交换系统（100）在分组交换机（140）中使用分组重组硬件（214），以在处理需要重新组装的传输分组（310）期间提高总体系统吞吐量。以这种方式，利用最少的处理器（110）干预来完成重组，而不必在重传之前将传输分组（310）的消息数据部分（312）复制到不同的存储器位置。

9. 发明授权

US5008938A Encryption apparatus 失效
标题翻译：加密装置
公开(公告)号：US5008938A
公开(公告)日：1991-04-16
申请号：US490900
申请日：1990-03-09
申请人： Thomas A. Freeburg , Richard E. White
发明人： Thomas A. Freeburg , Richard E. White
IPC分类号： H04L9/24 , H04L9/18
CPC分类号： H04L9/065 , H04L2209/12
摘要： An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
摘要翻译：一种以大致零延迟运行的加密电路。使用可编程键和多项式，可以不断更改加密算法以阻止任何非预期的接收方解码数据。密钥（101）和多项式（102）被加载到寄存器中。然后将密钥加载到移位寄存器中，并以可编程速率移位XOR门（106）。 XOR门的另一个输入来自于（103）禁用信号，多项式寄存器（102）和移位寄存器（104）的最后一级的结果。移位寄存器输出的8位将与要加密的输入数据进行异或运算。这些XOR门（105）的输出是加密数据。

10. 发明授权

US5103467A Asynchronous voice reconstruction for a digital communication system 失效
标题翻译：用于数字通信系统的异步语音重建
公开(公告)号：US5103467A
公开(公告)日：1992-04-07
申请号：US429599
申请日：1989-10-31
申请人： Greogory J. Bedlek , Richard E. White , Thomas A. Freeburg
发明人： Greogory J. Bedlek , Richard E. White , Thomas A. Freeburg
IPC分类号： G06F5/10 , H04J3/06 , H04L25/05
CPC分类号： G06F5/10 , H04J3/0626 , H04L25/05 , G06F2205/062 , G06F2205/104
摘要： A method and apparatus for performing the asynchronous reconstruction of a digital data stream is disclosed. An input data stream having an input rate, such as digitized speech, is stored in a circular buffer. Within the buffer, read and write marker positions are determined. Upon subsequent retrieval of the data stream at an output rate, data is taken from the position of the read marker each time data is written to the position of the write marker. Of importance, the read and write marker positions are determined such that they provide a delay greater than the difference between the input rate and the output rate over the length of the buffer. The data stream processing is then modified by ignoring at least some of the data stream when the input rate is faster than the output rate, and repeating at least some of the data stream when the input rate is slower than the output rate. In this manner a method of digitized voice reconstruction without reliance upon network synchronizatin is achieved.

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