专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08868975B2 Testing and operating a multiprocessor chip with processor redundancy 有权
标题翻译：测试和操作具有处理器冗余的多处理器芯片
公开(公告)号：US08868975B2
公开(公告)日：2014-10-21
申请号：US13196459
申请日：2011-08-02
申请人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
发明人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
IPC分类号： G06F11/00 , G06F11/22 , G06F11/20
CPC分类号： G06F11/2242 , G06F11/202
摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
摘要翻译：一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。片上逻辑根据所选的物理到逻辑映射配置处理器内核。

2. 发明申请

US20130031418A1 TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY 有权
标题翻译：测试和操作具有处理器冗余的多处理器芯片
公开(公告)号：US20130031418A1
公开(公告)日：2013-01-31
申请号：US13196459
申请日：2011-08-02
申请人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
发明人： Ralph E. Bellofatto , Steven M. Douskey , Rudolf A. Haring , Moyra K. McManus , Martin Ohmacht , Dietmar Schmunkamp , Krishnan Sugavanam , Bryan J. Weatherford
IPC分类号： G06F11/28
CPC分类号： G06F11/2242 , G06F11/202
摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
摘要翻译：一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。片上逻辑根据所选的物理到逻辑映射配置处理器内核。

3. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

5. 发明申请

US20090006808A1 ULTRASCALABLE PETAFLOP PARALLEL SUPERCOMPUTER 失效
标题翻译：超声波PETAFLOP并行超级计算机
公开(公告)号：US20090006808A1
公开(公告)日：2009-01-01
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/17337
摘要： A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的一种新型大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供了新的使用DMA引擎来促进节点之间的消息传递，而不需要节点处理资源。

6. 发明授权

US07761687B2 Ultrascalable petaflop parallel supercomputer 失效
标题翻译：超平面petaflop平行超级计算机
公开(公告)号：US07761687B2
公开(公告)日：2010-07-20
申请号：US11768905
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
发明人： Matthias A. Blumrich , Dong Chen , George Chiu , Thomas M. Cipolla , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Shawn Hall , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Martin Ohmacht , Valentina Salapura , Krishnan Sugavanam , Todd Takken
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.
摘要翻译： petaOPS规模的大规模并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括具有多达四个处理元件的单个专用集成电路（ASIC）。 ASIC节点通过多个独立网络互连，以最小的延迟最大化节点之间的数据包通信的吞吐量。多个网络可以包括用于并行算法消息传递的三个高速网络，包括Torus，集合网络和提供全局障碍和通知功能的全球异步网络。这些多个独立网络可以根据用于优化算法处理性能的算法的需求或阶段来协同或独立地利用。提供DMA引擎的使用以促进节点之间的消息传递，而不需要节点处理资源。

7. 发明授权

US08806141B2 List based prefetch 有权
标题翻译：基于列表的预取
公开(公告)号：US08806141B2
公开(公告)日：2014-08-12
申请号：US13593838
申请日：2012-08-24
申请人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter Boyle , Norman Christ , Alan Gara , Changhoan Kim , Robert Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
摘要翻译：列表预取引擎提高并行计算系统的性能。列表预取引擎接收当前高速缓存未命中地址。列表预取引擎评估当前缓存未命中地址是否有效。如果当前高速缓存未命中地址有效，则列表预取引擎将比较当前高速缓存未命中地址和列表地址。列表地址表示列表中的地址。列表描述了先前高速缓存未命中地址的任意序列。如果当前缓存未命中地址和列表地址之间存在匹配，则预取引擎将根据列表预取数据。

8. 发明授权

US08370551B2 Arbitration in crossbar interconnect for low latency 失效
标题翻译：交叉开关中的仲裁用于低延迟
公开(公告)号：US08370551B2
公开(公告)日：2013-02-05
申请号：US12684287
申请日：2010-01-08
申请人： Martin Ohmacht , Krishnan Sugavanam
发明人： Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F13/00 , G06F13/36 , G06F13/368
CPC分类号： G06F13/1657
摘要： A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.
摘要翻译：一种用于减少通过交叉开关传送的信号的等待时间的系统和方法和计算机程序产品，所述方法包括在与从属设备相关联的从属仲裁逻辑设备处使用来自一个或多个主设备的访问请求的两个或多个优先权向量信号在每个时钟周期中循环使用，用于选择一个请求主设备，并更新每个时钟周期使用的各个优先级向量信号。类似地，从一个或多个从设备请求访问的每个主机可以具有两个或更多个优先级向量，并且可以在每个时钟周期之间循环，以进一步减少延迟并通过交叉开关提高吞吐量性能。

9. 发明申请

US20110173422A1 PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN 失效
标题翻译：暂停处理器硬件螺纹密码
公开(公告)号：US20110173422A1
公开(公告)日：2011-07-14
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/44 , G06F15/00 , G06F9/06
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

10. 发明申请

US20110173357A1 ARBITRATION IN CROSSBAR INTERCONNECT FOR LOW LATENCY 失效
标题翻译：低边界交叉连接中的仲裁
公开(公告)号：US20110173357A1
公开(公告)日：2011-07-14
申请号：US12684287
申请日：2010-01-08
申请人： Martin Ohmacht , Krishnan Sugavanam
发明人： Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F13/40 , G06F13/368 , G06F13/37
CPC分类号： G06F13/1657
摘要： A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.
摘要翻译：一种用于减少通过交叉开关传送的信号的等待时间的系统和方法和计算机程序产品，所述方法包括在与从属设备相关联的从属仲裁逻辑设备处使用来自一个或多个主设备的访问请求的两个或多个优先权向量信号在每个时钟周期中循环使用，用于选择一个请求主设备，并更新每个时钟周期使用的各个优先级向量信号。类似地，从一个或多个从设备请求访问的每个主机可以具有两个或更多个优先级向量，并且可以在每个时钟周期之间循环，以进一步减少延迟并通过交叉开关提高吞吐量性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式