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1. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

2. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

3. 发明申请

US20110173422A1 PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN 失效
标题翻译：暂停处理器硬件螺纹密码
公开(公告)号：US20110173422A1
公开(公告)日：2011-07-14
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/44 , G06F15/00 , G06F9/06
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

4. 发明授权

US08447960B2 Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition 失效
标题翻译：通过外部逻辑监视轮询循环退出时间条件，在引脚断言时暂停和激活线程状态
公开(公告)号：US08447960B2
公开(公告)日：2013-05-21
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/48
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

5. 发明申请

US20110173420A1 PROCESSOR RESUME UNIT 审中-公开
标题翻译：处理器修复单元
公开(公告)号：US20110173420A1
公开(公告)日：2011-07-14
申请号：US12684852
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3877 , G06F9/3885
摘要： A system for enhancing performance of a computer includes a computer system having a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processor. An external unit is external to the processor for monitoring specified computer resources. The external unit is configured to detect a specified condition using the processor. The processor including one or more threads. The thread resumes an active state from a pause state using the external unit when the specified condition is detected by the external unit.
摘要翻译：一种用于增强计算机性能的系统包括具有数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，并且程序的步骤由处理器执行。处理器外部的外部单元用于监视指定的计算机资源。外部单元配置为使用处理器检测指定的条件。处理器包括一个或多个线程。当外部单元检测到指定的条件时，线程将使用外部单元从暂停状态恢复活动状态。

6. 发明授权

US08595389B2 Distributed performance counters 失效
标题翻译：分布式性能计数器
公开(公告)号：US08595389B2
公开(公告)日：2013-11-26
申请号：US12684738
申请日：2010-01-08
申请人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
发明人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
IPC分类号： G06F13/00 , G06F3/00 , G06F11/00
CPC分类号： G06F13/4247 , G06F9/30145 , G06F11/3476 , G06F11/348 , G06F11/3495 , G06F12/0897 , G06F2201/88 , G06F2221/2117
摘要： A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
摘要翻译：多个第一性能计数器模块耦合到多个处理核心。多个第一性能计数器模块可操作以分别收集与多个处理核心相关联的性能数据。多个第二性能计数器模块耦合到多个L2高速缓存单元，并且所述多个第二性能计数器模块可操作以分别收集与所述多个L2高速缓存单元相关联的性能数据。中央性能计数器模块可以用于协调来自多个第一性能计数器模块和多个第二性能模块的计数器数据，中央性能计数器模块，多个第一性能计数器模块和多个第二性能计数器模块通过菊花链连接连接。

7. 发明申请

US20110172968A1 DISTRIBUTED PERFORMANCE COUNTERS 失效
标题翻译：分布式性能计数器
公开(公告)号：US20110172968A1
公开(公告)日：2011-07-14
申请号：US12684738
申请日：2010-01-08
申请人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
发明人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
IPC分类号： G21C17/00
CPC分类号： G06F13/4247 , G06F9/30145 , G06F11/3476 , G06F11/348 , G06F11/3495 , G06F12/0897 , G06F2201/88 , G06F2221/2117
摘要： A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
摘要翻译：多个第一性能计数器模块耦合到多个处理核心。多个第一性能计数器模块可操作以分别收集与多个处理核心相关联的性能数据。多个第二性能计数器模块耦合到多个L2高速缓存单元，并且所述多个第二性能计数器模块可操作以分别收集与所述多个L2高速缓存单元相关联的性能数据。中央性能计数器模块可以用于协调来自多个第一性能计数器模块和多个第二性能模块的计数器数据，中央性能计数器模块，多个第一性能计数器模块和多个第二性能计数器模块通过菊花链连接连接。

8. 发明授权

US08713294B2 Heap/stack guard pages using a wakeup unit 失效
标题翻译：堆/堆栈保护页面使用唤醒单元
公开(公告)号：US08713294B2
公开(公告)日：2014-04-29
申请号：US12696817
申请日：2010-01-29
申请人： Thomas M. Gooding , David L. Satterfield , Burkhard Steinmacher-Burow
发明人： Thomas M. Gooding , David L. Satterfield , Burkhard Steinmacher-Burow
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F15/17381 , G06F9/30072
摘要： A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
摘要翻译：一种用于在处理器上提供存储器访问检查的方法和系统，包括以下步骤：使用唤醒单元检测对包括一级高速缓存的存储设备的访问。该方法包括使对应于保护页面的1级缓存范围失效，以及配置多个唤醒地址比较（WAC）寄存器以允许访问所选择的WAC寄存器。该方法选择多个WAC寄存器中的一个，并建立与保护页相关的WAC寄存器。该方法配置唤醒单元在所选WAC寄存器访问时中断。当防护页被违反时，该方法使用唤醒单元检测存储设备的访问。该方法使用唤醒单元为内核生成中断，并确定中断源。该方法检测分配给违规保护页面的激活的WAC寄存器，并发起响应。

9. 发明申请

US20110119445A1 HEAP/STACK GUARD PAGES USING A WAKEUP UNIT 失效
标题翻译： HEAP / STACK GUARD页面使用唤醒单元
公开(公告)号：US20110119445A1
公开(公告)日：2011-05-19
申请号：US12696817
申请日：2010-01-29
申请人： Thomas M. Gooding , David L. Satterfield , Burkhard Steinmacher-Burow
发明人： Thomas M. Gooding , David L. Satterfield , Burkhard Steinmacher-Burow
IPC分类号： G06F12/08 , G06F12/00 , G06F13/24
CPC分类号： G06F15/17381 , G06F9/30072
摘要： A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.
摘要翻译：一种用于在处理器上提供存储器访问检查的方法和系统，包括以下步骤：使用唤醒单元检测对包括一级高速缓存的存储设备的访问。该方法包括使对应于保护页面的1级缓存范围失效，以及配置多个唤醒地址比较（WAC）寄存器以允许访问所选择的WAC寄存器。该方法选择多个WAC寄存器中的一个，并建立与保护页相关的WAC寄存器。该方法配置唤醒单元在所选WAC寄存器访问时中断。当防护页被违反时，该方法使用唤醒单元检测存储设备的访问。该方法使用唤醒单元为内核生成中断，并确定中断源。该方法检测分配给违规保护页面的激活的WAC寄存器，并发起响应。

10. 发明申请

US20110172969A1 OPCODE COUNTING FOR PERFORMANCE MEASUREMENT 失效
标题翻译：用于性能测量的操作码计数
公开(公告)号：US20110172969A1
公开(公告)日：2011-07-14
申请号：US12688773
申请日：2010-01-15
申请人： Alan Gara , David L. Satterfield , Robert E. Walkup
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F15/00
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
摘要翻译：公开了用于测量在处理系统的处理单元上运行的程序的性能的方法，系统和计算机程序产品。在一个实施例中，该方法包括通知处理单元执行的程序中的每个指令的逻辑单元，向每个指令分配权重，将指令分配给多个组，以及分析多个组以测量一个或更多指标。在一个实施例中，每个指令包括操作代码部分，并且分配包括基于指令的操作代码部分将指令分配给组。在一个实施例中，每种类型的指令被分配给多个组中的相应一个组。这些组可以组合成多个组的组。

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