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1. 发明授权

US08001401B2 Power throttling of collections of computing elements 失效
标题翻译：功率节流计算元件的集合
公开(公告)号：US08001401B2
公开(公告)日：2011-08-16
申请号：US11768752
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
发明人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/206
摘要： An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
摘要翻译：用于控制计算机中的电力使用的装置和方法包括与本地控制装置通信的多个计算机，以及向本地控制装置和计算机供电的电源。多个传感器与计算机通信以确定计算机的功率使用，并且系统控制装置与计算机通信以控制计算机的电力使用。

2. 发明申请

US20090006873A1 POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS 失效
标题翻译：计算元素收集的功率曲线
公开(公告)号：US20090006873A1
公开(公告)日：2009-01-01
申请号：US11768752
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
发明人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/206
摘要： An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
摘要翻译：用于控制计算机中的电力使用的装置和方法包括与本地控制装置通信的多个计算机，以及向本地控制装置和计算机供电的电源。多个传感器与计算机通信以确定计算机的功率使用，并且系统控制装置与计算机通信以控制计算机的电力使用。

3. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

4. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

5. 发明授权

US06961782B1 Methods for routing packets on a linear array of processors 失效
公开(公告)号：US06961782B1
公开(公告)日：2005-11-01
申请号：US09525707
申请日：2000-03-14
申请人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
发明人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： G06F15/17381 , G06F15/17337
摘要： There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

6. 发明授权

US5664223A System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively 失效
标题翻译：使用分别耦合在FIFO缓冲器和两个独立总线之间的两个独立控制的DMA引擎来独立传输数据的系统
公开(公告)号：US5664223A
公开(公告)日：1997-09-02
申请号：US223144
申请日：1994-04-05
申请人： Carl A. Bender , Gerard M. Salem , Richard A. Swetz , Singpui Zee , Ben J. Nathanson
发明人： Carl A. Bender , Gerard M. Salem , Richard A. Swetz , Singpui Zee , Ben J. Nathanson
IPC分类号： G06F13/36 , G06F1/04 , G06F13/28 , G06F3/00
CPC分类号： G06F13/28
摘要： An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.
摘要翻译：一种用于在主处理器及其存储器之间传送数据和分组交换机的装置包括耦合到主处理器及其存储器的第一总线，耦合在第一总线和第二总线之间的双向先进先出（FIFO）缓冲器总线，并且具有连接到第一总线的第一端口和连接到第二总线的第二端口，耦合到第二总线的通信处理器，可操作地耦合到第二总线的存储器，第一直接存储器访问（DMA）引擎耦合在第一总线和FIFO缓冲器之间，用于在主处理器和FIFO缓冲器之间传送数据;耦合在FIFO缓冲器和第二总线之间的第二直接存储器访问（DMA）引擎，用于在FIFO缓冲器和第二总线之间传送数据以及可操作地耦合在第二总线和开关之间的分组交换接口，用于将第二总线与交换机接口，其中分组在主处理器的存储器和根据通信协议切换，并且其中第一和第二DMA引擎相互独立地传送数据包的数据。

7. 发明授权

US5213272A Environmental non-powered pail type trash container 失效
标题翻译：环保无动力桶式垃圾桶
公开(公告)号：US5213272A
公开(公告)日：1993-05-25
申请号：US913930
申请日：1992-07-17
申请人： Denis Gallagher , Richard A. Swetz
发明人： Denis Gallagher , Richard A. Swetz
IPC分类号： B02C18/00 , B30B9/30 , B65F1/00 , B65F1/14
CPC分类号： B02C18/0084 , B02C19/0081 , B30B9/30 , B30B9/323 , B65F1/0033 , B65F1/1405 , B65F2210/1525 , Y02W30/10 , Y02W30/60 , Y10S241/38
摘要： A segregated waste disposal device is disclosed which includes a plurality of waste receptacles provided in a main housing, each of the plurality of waste receptacles receiving one of a plurality of distinct waste products, respectively, including glass and metal. An opening within the main housing receives at least one of the glass and metal waste, and the weighted lid connected to the main housing crushes waste deposited into the opening. The lid may be opened either by hydraulic or mechanical spring mechanisms and a grate member provided within the opening and beneath the weighted lid allows crushed glass to free-fall therethrough into a predetermined receptacle. A sweep arm sweeps remaining crushed waste off of the grate into a waste receptacle other than a waste receptacle containing crushed glass.
摘要翻译：公开了一种分离的废物处理装置，其包括设置在主壳体中的多个废物容器，所述多个废物容纳容器中的每一个容纳多个不同的废物产品中的一个，分别包括玻璃和金属。主壳体内的开口接收玻璃和金属废物中的至少一个，并且连接到主壳体的加重盖将粉碎沉积到开口中的废物。盖可以通过液压或机械弹簧机构打开，并且设置在开口内并且在加重的盖子下方的格栅构件允许碎玻璃从其中自由落下到预定的容器中。清扫臂将残留的碎屑从炉排中除去除了含有碎玻璃的废物容器之外的废物容器。

8. 发明授权

US07619993B2 Efficient probabilistic duplicate packet detector in computer networks 失效
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US07619993B2
公开(公告)日：2009-11-17
申请号：US11264529
申请日：2005-11-01
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/28 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , G08C25/00 , G06F15/16
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

9. 发明授权

US5139205A Segregated waste disposal system 失效
标题翻译：分离废物处理系统
公开(公告)号：US5139205A
公开(公告)日：1992-08-18
申请号：US729362
申请日：1991-07-12
申请人： Denis Gallagher , Richard A. Swetz
发明人： Denis Gallagher , Richard A. Swetz
IPC分类号： B02C18/00 , B30B9/30
CPC分类号： B65F1/0033 , B02C18/0007 , B02C18/0084 , B02C19/0081 , B30B9/30 , B65F2001/008 , B65F2210/148 , Y02W30/10 , Y02W30/60
摘要： A segregated waste disposal system is disclosed which includes a plurality of separate bins for receiving paper, plastics, glass, and metal respectively. Two openings are provided within the overall unit, one of the openings receiving paper/plastics, the other opening receiving glass/metal. The respective openings perform different disposal functions with respect to the materials inserted therein, whereby the glass/metals opening compresses the glass/metals such that the compressed glass will immediately fall through a grate into a glass bin and a sweep arm sweeps compressed metal to an adjacent metals bin. The paper/plastics opening compresses the paper/plastic and subsequently shreds the compressed material. Deflection to a respective paper/plastics bin is determined by an operators instruction achieved via a selection panel provided in connection with the waste disposal system.
摘要翻译：公开了一种分离的废物处理系统，其包括分别用于接收纸，塑料，玻璃和金属的多个分开的箱。在整个单元内设置两个开口，其中一个开口接收纸/塑料，另一个开口接收玻璃/金属。各个开口相对于插入其中的材料执行不同的处理功能，由此玻璃/金属开口压缩玻璃/金属，使得压缩玻璃将立即通过格栅落入玻璃箱中，并且扫掠臂将压缩的金属扫过相邻金属仓。纸/塑料开口压缩纸/塑料，随后将压缩材料切碎。通过经由与废物处理系统相关联的选择面板实现的操作者指令来确定对相应纸/塑料仓的偏转。

10. 发明授权

US08031639B2 Efficient probabilistic duplicate packet detector in computer networks 有权
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US08031639B2
公开(公告)日：2011-10-04
申请号：US12561669
申请日：2009-09-17
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/28 , H04L1/00 , H04L12/26 , G01R31/08 , G06F11/00 , G06F15/16 , G08C15/00 , G08C25/00 , H04J1/16 , H04J3/14
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

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