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1. 发明授权

US07619993B2 Efficient probabilistic duplicate packet detector in computer networks 失效
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US07619993B2
公开(公告)日：2009-11-17
申请号：US11264529
申请日：2005-11-01
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/28 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , G08C25/00 , G06F15/16
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

2. 发明授权

US08031639B2 Efficient probabilistic duplicate packet detector in computer networks 有权
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US08031639B2
公开(公告)日：2011-10-04
申请号：US12561669
申请日：2009-09-17
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/28 , H04L1/00 , H04L12/26 , G01R31/08 , G06F11/00 , G06F15/16 , G08C15/00 , G08C25/00 , H04J1/16 , H04J3/14
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

3. 发明申请

US20100008251A1 EFFICIENT PROBABILISTIC DUPLICATE PACKET DETECTOR IN COMPUTER NETWORKS 有权
标题翻译：计算机网络中高效的可复用双重分组检测器
公开(公告)号：US20100008251A1
公开(公告)日：2010-01-14
申请号：US12561669
申请日：2009-09-17
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama K. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/26
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

4. 发明授权

US06381643B1 Mechanism and procedure for detecting switch mis-cabling 失效
标题翻译：检测开关错误布线的机制和程序
公开(公告)号：US06381643B1
公开(公告)日：2002-04-30
申请号：US09435545
申请日：1999-11-08
申请人： Robert F. Bartfai , Carl A. Bender , Jay R. Herring , Nicholas P. Rash , Kevin J. Reilly
发明人： Robert F. Bartfai , Carl A. Bender , Jay R. Herring , Nicholas P. Rash , Kevin J. Reilly
IPC分类号： G06F16163
CPC分类号： H04Q3/685 , H04L43/50 , H04L45/34 , H04M3/2254 , H04Q1/24 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13166 , H04Q2213/13322 , H04Q2213/1334
摘要： A method, and a system for implementing the method, for implementing the method, for determining if a wire has been miswired in a network comprising service nodes and switch elements. The method includes the steps of: (1) transmitting a transmission stream in an outbound route, (where this transmission stream includes one or more service node fields for one or more service nodes, one or more switch element fields for one or more switch elements connected to the one or more service nodes, and a port field for each the switch element); (2) if the transmission stream is received on a port at a the switch element different than a the port field for the switch element indicated by the transmission stream, then setting an error indicator in the transmission stream; (3) transmitting the transmission stream back to the one or more service nodes in a return route, where the one or more service nodes determine from the error indicator a miswired condition between the receiving switch element and a previous switch element or service node along the outbound route. The one or more service nodes can record, store and tabulate the miswired condition and one or more additional miswired conditions. The transmission stream can store the one or more switch element fields for the one or more switch elements and the port fields for each the switch element separately for a path comprising the outbound route and a path comprising the return route.
摘要翻译：一种用于实现该方法的方法和系统，用于确定在包括服务节点和交换元件的网络中线是否已被误接线。该方法包括以下步骤：（1）在出站路由（其中该传输流包括一个或多个服务节点的一个或多个服务节点字段）中传送一个或多个开关元件字段用于一个或多个开关元件连接到一个或多个服务节点，以及每个开关元件的端口字段）; （2）如果在与由传输流指示的开关元件的端口字段不同的开关元件的端口上接收到传输流，则在传输流中设置错误指示符; （3）在返回路由中将所述传输流发送回所述一个或多个服务节点，其中所述一个或多个服务节点从所述错误指示符确定所述接收交换机元件与所述接收交换机元件之间的先前交换元件或服务节点之间的连线条件出站路线一个或多个服务节点可以记录，存储和制表误接线条件以及一个或多个附加的误接线条件。传输流可以为包括出站路由的路径和包括返回路由的路径分别存储用于每个交换机元件的一个或多个交换元件的一个或多个交换单元字段和端口字段。

5. 发明授权

US07539772B2 Method for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables 失效
标题翻译：用于通过使用多种类型的转发表的数据传送网络的节点来促进数据分组转发的方法
公开(公告)号：US07539772B2
公开(公告)日：2009-05-26
申请号：US11841163
申请日：2007-08-20
申请人： Jay R. Herring , Scot H. Rider
发明人： Jay R. Herring , Scot H. Rider
IPC分类号： G06F15/173
CPC分类号： H04L45/742 , H04L45/00 , H04L45/54
摘要： A method is provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.
摘要翻译：提供了一种通过采用不同类型的转发表来将接收到的下游节点和上游节点的数据分组映射到交换节点的适当输出端口来减少交换节点的转发表所需的存储器的大小的方法。该方法包括在网络的数据传输节点处接收数据分组，并且基于与接收到的数据分组相关联的属性，从节点可访问的多种类型的转发表中选择转发表，并将数据分组映射到输出端口基于与分组关联的属性，利用从多种类型的转发表中选择的转发表来使用该节点。

6. 发明申请

US20080205278A1 METHOD FOR ACTIVELY MANAGING CENTRAL QUEUE BUFFER ALLOCATION 失效
标题翻译：用于主动管理中央队列缓冲区分配的方法
公开(公告)号：US20080205278A1
公开(公告)日：2008-08-28
申请号：US12105570
申请日：2008-04-18
申请人： Derrick L. Garmire , Jay R. Herring , Ronald A. Linton , Scot H. Rider
发明人： Derrick L. Garmire , Jay R. Herring , Ronald A. Linton , Scot H. Rider
IPC分类号： H04L12/24
CPC分类号： H04L49/9063 , H04L49/3036 , H04L49/3045 , H04L49/90 , H04L49/9057 , H04L49/9078
摘要： A method is provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.
摘要翻译：提供了一种用于数据传输网络的交换节点的分组流控制的方法。该方法包括基于当前在中央队列中可用的未使用空间的量，主动地管理分配给交换节点的端口的交换节点的中心队列中的空间分配。在另一方面，该方法包括分别跟踪未分配的空间和空闲的分配空间，其已被用于缓冲由端口接收的分组，但是由于从中央队列中移除分组而进行的先前的管理更新。每个端口都提供空闲空间，目前分配给该端口和中央队列中当前未分配空间的数量，以分配到端口的一个或多个虚拟通道。

7. 发明授权

US07058866B2 Method and system for an on-chip AC self-test controller 失效
标题翻译：一种片上AC自检控制器的方法和系统
公开(公告)号：US07058866B2
公开(公告)日：2006-06-06
申请号：US10131554
申请日：2002-04-24
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.
摘要翻译：一种用于在集成电路上执行AC自检的方法，包括在正常操作期间使用的系统时钟。该方法包括响应于系统时钟将长数据捕获脉冲施加到第一测试寄存器，并且响应于系统时钟进一步将速度数据发射脉冲施加到第一测试寄存器。响应于将速度数据发射脉冲应用于第一测试寄存器，将数据从第一寄存器输入到逻辑路径。响应于系统时钟，将速度数据采集脉冲应用到第二个测试寄存器。响应于将速度数据捕获脉冲施加到第二寄存器，将逻辑路径的输出输入到第二测试寄存器。将响应系统时钟的长数据发射脉冲应用于第二个测试寄存器。

8. 发明授权

US07596734B2 On-Chip AC self-test controller 有权
标题翻译：片上AC自检控制器
公开(公告)号：US07596734B2
公开(公告)日：2009-09-29
申请号：US12185172
申请日：2008-08-04
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.
摘要翻译：提供了一种用于在包括用于正常操作的系统时钟的集成电路上执行AC自检的系统。该系统包括系统时钟，自检电路，第一和第二测试寄存器，用于响应于数据脉冲序列捕获和发射测试数据，以及待测试的逻辑电路。自检电路包括一个交流自检控制器和时钟分离器。时钟分配器产生数据脉冲序列，包括长数据捕获脉冲，随后是速度数据发射脉冲和速度数据捕获脉冲，随后是长数据发射脉冲。为系统时钟的公共周期产生速度数据发射脉冲和速度数据捕获脉冲。

9. 发明授权

US07308505B2 Method, system and program product for facilitating forwarding of data packets through a node of a data transfer network using multiple types of forwarding tables 失效
标题翻译：方法，系统和程序产品，用于通过使用多种转发表的数据传输网络的节点促进数据分组的转发
公开(公告)号：US07308505B2
公开(公告)日：2007-12-11
申请号：US10737989
申请日：2003-12-17
申请人： Jay R. Herring , Scot H. Rider
发明人： Jay R. Herring , Scot H. Rider
IPC分类号： G06F15/173
CPC分类号： H04L45/742 , H04L45/00 , H04L45/54
摘要： Method, system and program product are provided for reducing size of memory required for a switching node's forwarding table by employing forwarding tables of different types to map received data packets addressed to downstream nodes and upstream nodes to appropriate output ports of the switching node. The method includes receiving a data packet at a data transfer node of a network and selecting a forwarding table from multiple types of forwarding tables accessible by the node based on an attribute associated with the received data packet, and mapping the data packet to an output port of the node utilizing the forwarding table selected from the multiple types of forwarding tables based on the attribute associated with the packet.
摘要翻译：提供方法，系统和程序产品，用于通过采用不同类型的转发表来将接收到的下游节点和上游节点的数据分组映射到交换节点的适当输出端口来减少交换节点的转发表所需的存储器的大小。该方法包括在网络的数据传输节点处接收数据分组，并且基于与接收到的数据分组相关联的属性，从节点可访问的多种类型的转发表中选择转发表，并将数据分组映射到输出端口基于与分组关联的属性，利用从多种类型的转发表中选择的转发表来使用该节点。

10. 发明授权

US07146587B2 Scalable logic self-test configuration for multiple chips 失效
标题翻译：可扩展的逻辑自检配置为多个芯片
公开(公告)号：US07146587B2
公开(公告)日：2006-12-05
申请号：US10753852
申请日：2004-01-08
申请人： Marvin J. Rich , Jay R. Herring
发明人： Marvin J. Rich , Jay R. Herring
IPC分类号： G06F17/50
CPC分类号： G01R31/318594
摘要： A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.
摘要翻译：可扩展的LBIST控制结构提供了测试芯片内和/或跨多个芯片的多个独立时钟域。 LBIST控制结构通过LBIST序列的每个步骤同步地排列所有时钟域，允许从公共点控制多个时钟域和/或多个芯片。

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