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1. 发明授权

US06961782B1 Methods for routing packets on a linear array of processors 失效
公开(公告)号：US06961782B1
公开(公告)日：2005-11-01
申请号：US09525707
申请日：2000-03-14
申请人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
发明人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： G06F15/17381 , G06F15/17337
摘要： There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

2. 发明授权

US07477608B2 Methods for routing packets on a linear array of processors 失效
标题翻译：在线性阵列处理器上路由数据包的方法
公开(公告)号：US07477608B2
公开(公告)日：2009-01-13
申请号：US11186693
申请日：2005-07-21
申请人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
发明人： Monty M. Denneau , Peter H. Hochschild , Richard A. Swetz , Henry S. Warren, Jr.
IPC分类号： H04L12/26 , H04L12/66 , G06F15/00
CPC分类号： G06F15/17381 , G06F15/17337
摘要： There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.
摘要翻译：提供了一种用于在以最近邻配置连接的N个处理器的线性上路由分组的方法。该方法包括对于阵列的每个终端处理器将未使用的输出连接到相应的未使用的输入的步骤。对于将数据包从源直接路由到目标处理器所需的每个轴，执行以下步骤。确定是否将分组从初始处理器直接发送到目标处理器的结果分别小于或大于N / 2移动。初始处理器是第一个轴中的源处理器，目标处理器是最后一个轴上的目标处理器。当结果小于N / 2移动时，数据包从初始处理器直接发送到目标处理器。当结果大于N / 2移动时，数据包被间接发送以便包围每个终端处理器。该方法可以可选地包括当结果等于N / 2移动并且N是偶数时，使用任一发送步骤随机发送分组的步骤。

3. 发明授权

US5414740A Synchronous communication system having multiplexed information transfer and transition phases 失效
标题翻译：同步通信系统具有复用的信息传输和转换阶段
公开(公告)号：US5414740A
公开(公告)日：1995-05-09
申请号：US992200
申请日：1992-12-17
申请人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
发明人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
IPC分类号： G06F13/00 , G06F13/38 , H04L7/00 , H04L29/14
CPC分类号： G06F13/385
摘要： A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver. A synchronizer may be provided for synchronizing occurrences of information transfer phases of the first communication station with occurrences of corresponding information transfer phases of the second communication station to a synchronization offset X equal to the number of clock periods of the system clock by which occurrences of each phase of the second communication station lag occurrences of the corresponding phase of the first communication station.
摘要翻译：具有相位复用的通信系统段。第一通信站包含在一系列时钟周期期间顺序地输出一系列数据信号的数据源。数据源在每个时钟周期期间从串联输出一个数据信号。第一通信站还包含具有连接到数据源的输出的输入的转换缓冲器。转换缓冲器具有先入先出模式，其中转换缓冲器存储在最近的Q个时钟周期期间从数据源输出的一系列Q数据信号，其中Q是大于零的整数。第二通信站包括在一系列时钟周期期间顺序地输入一系列数据信号的数据接收器。数据接收器在每个时钟周期期间从串联输入一个数据信号。通信线将数据源的输出连接到数据接收器的输入。可以提供同步器，用于将第一通信站的信息传送阶段的出现与第二通信站的相应信息传送阶段的出现同步到等于系统时钟的时钟周期数的同步偏移X，同步偏移X通过每个第二通信站的相位滞后于第一通信站的相应阶段。

4. 发明授权

US4914612A Massively distributed simulation engine 失效
标题翻译：大规模分布式仿真引擎
公开(公告)号：US4914612A
公开(公告)日：1990-04-03
申请号：US175879
申请日：1988-03-31
申请人： Daniel K. Beece , Monty M. Denneau , Peter H. Hochschild , Allan Rappaport , Cynthia A. Trempel
发明人： Daniel K. Beece , Monty M. Denneau , Peter H. Hochschild , Allan Rappaport , Cynthia A. Trempel
IPC分类号： G06F11/25 , G06F9/455 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5022
摘要： A simulation engine for logically simulating a logic network, which is divided into several levels of hierarchy. At the lowest level is a logic chip which has stored in an instruction memory a sequentially executed program of logical operators and operand addresses. The operand addresses refer to an input memory of the chip. The next highest level is the logic unit, on one circuit board, comprising a plurality of such logic chips. Each of the logic chips of the unit has its input memory receiving the same data from an input bus and a local bus and provides as its output one of the bits of an output bus and one of the bits of the local bus. At the next level, called a cluster, several logic units have their input and output buses interconnected by a plurality of switch units. All the logic chips of the several logic units operate in parallel with the exchange of data through the switch units. Several clusters can be combined into a super cluster by connecting together two or more sets of switch units.

5. 发明授权

US5546391A Central shared queue based time multiplexed packet switch with deadlock avoidance 失效
标题翻译：基于中心共享队列的时间复用分组交换机具有死锁避免
公开(公告)号：US5546391A
公开(公告)日：1996-08-13
申请号：US424824
申请日：1995-04-19
申请人： Peter H. Hochschild , Monty M. Denneau
发明人： Peter H. Hochschild , Monty M. Denneau
IPC分类号： G06F15/173 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/939 , H04Q11/04 , H04L12/56
CPC分类号： G06F15/17393 , G06F15/17381 , H04L49/103 , H04L49/3036 , H04Q11/0478 , H04L49/101 , H04L49/205 , H04L49/254 , H04L49/552
摘要： A packet switch (25.sub.1) contains input port circuits (310) and output port circuits (380) inter-connected through two parallel paths: a multi-slot central queue (350) and a low latency by-pass cross-point switching matrix (360). The central queue has one slot dedicated to each output port to store a message portion ("chunk") destined for only that output port with the remaining slots being shared for all the output ports and dynamically allocated thereamong, as the need arises. Only those chunks which are contending for the same output port are stored in the central queue; otherwise, these chunks are routed to the appropriate output ports through the cross-point switching matrix. Each receiver classifies its resident chunks (as critical or non-critical) based upon both the urgency with which that chunk must be transmitted to its destination output port and by the status of the central queue. A critical chunk, i.e. one that must be transported as soon as possible to an output port is stored within the dedicated slot for that particular output port. Non-critical chunks are stored within available shared slots in the central queue. Independent least recently used arbiters (368, 385) separately control read and write access to the central queue based upon requests for service issued by input and output port circuits in order to impart assure fair access by each of these ports.
摘要翻译：分组交换机（251）包含通过两个并行路径互连的输入端口电路（310）和输出端口电路（380）：多时隙中心队列（350）和低等待时间旁路交叉点交换矩阵 360）。中央队列具有专用于每个输出端口的一个时隙，用于存储目的地仅仅是该输出端口的消息部分（“块”），其余时隙对于所有输出端口共享，并且根据需要动态地分配它们。只有那些竞争同一输出端口的块才存储在中央队列中; 否则，这些块通过交叉点交换矩阵路由到适当的输出端口。每个接收器基于必须发送到其目的地输出端口的紧急程度和中央队列的状态，将其驻留的块（作为关键或非关键）分类。一个关键的块，即必须尽快运送到输出端口的块被存储在该特定输出端口的专用槽内。非关键块存储在中央队列中的可用共享槽中。独立的最近最少使用的仲裁器（368,385）分别基于由输入和输出端口电路发出的服务请求来单独地控制对中央队列的读写访问，以便确保这些端口中的每个端口的公平访问。

6. 发明授权

US5371735A Communication network with non-unique device identifiers and method of establishing connection paths in such a network 失效
标题翻译：具有非唯一设备标识符的通信网络和在这种网络中建立连接路径的方法
公开(公告)号：US5371735A
公开(公告)日：1994-12-06
申请号：US026332
申请日：1993-03-04
申请人： Monty M. Denneau , Peter H. Hochschild , Craig B. Stunkel
发明人： Monty M. Denneau , Peter H. Hochschild , Craig B. Stunkel
IPC分类号： H04Q3/52 , G06F15/173 , H04L12/18 , H04L12/50 , H04J3/24
CPC分类号： G06F15/17393 , H04L12/18 , H04L12/50
摘要： A communication network having a service processor, a plurality of terminal nodes, and a network of switch nodes for switchably connecting the service processor to each terminal node by way of one or more connection paths. Each switch node in the communication network is connected to the service processor either directly or through one or more other switch nodes. Each terminal node of the communication network is connected to a switch node. Each switch node and each terminal node has a device identification. At least two nodes have the same device identification. Each target node having the same device identification as another node can preferably be connected to the service processor by way of at least one connection path which does not include any other node having the same device identification as the target node. All switch nodes having the same minimum connection path length may, for example, have the same device identification.
摘要翻译：具有服务处理器，多个终端节点和交换节点网络的通信网络，用于通过一个或多个连接路径可转换地将服务处理器连接到每个终端节点。通信网络中的每个交换节点直接或通过一个或多个其他交换节点连接到服务处理器。通信网络的每个终端节点连接到交换节点。每个交换节点和每个终端节点具有设备标识。至少有两个节点具有相同的设备标识。具有与另一节点相同的设备标识的每个目标节点可以优选地通过至少一个不包括与目标节点具有相同设备标识的其他节点的连接路径连接到服务处理器。具有相同最小连接路径长度的所有交换节点可以例如具有相同的设备标识。

7. 发明授权

US5414832A Tunable synchronous electronic communication apparatus 失效
标题翻译：可调同步电子通信装置
公开(公告)号：US5414832A
公开(公告)日：1995-05-09
申请号：US991930
申请日：1992-12-17
申请人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
发明人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
IPC分类号： G06F1/10 , H04L7/00 , H04L7/033 , H04L7/10 , G06F1/04
CPC分类号： H04L7/0091 , H04L7/0033 , H04L7/0041 , H04L7/10
摘要： A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+.DELTA.pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0
摘要翻译：可以调整同步通信装置以确保沿着传输线传播的信号的可靠接收。该装置可以用作高频，高度连接的同步网络中的通信端口，其中所有端口都可以由单个远程网络控制设备调谐。本地数据源在一系列本地时钟周期的每一个期间输出数据信号。本地源延迟电路从本地数据源接收输入数据信号，并相对于相应的输入数据信号输出延迟了所有量（mT + DELTA pT）的输出信号，其中m是正整数或零，其中0

8. 发明授权

US5566342A Scalable switch wiring technique for large arrays of processors 失效
标题翻译：用于大型处理器阵列的可扩展开关接线技术
公开(公告)号：US5566342A
公开(公告)日：1996-10-15
申请号：US298828
申请日：1994-08-31
申请人： Monty M. Denneau , Donald G. Grice , Peter H. Hochschild , Craig B. Stunkel
发明人： Monty M. Denneau , Donald G. Grice , Peter H. Hochschild , Craig B. Stunkel
IPC分类号： G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17393
摘要： Connections between the node switch sets associated with processors in large scalable processor arrays, such as those of the butterfly variety, are arranged, like the 2-D mesh array, in rows and columns between the node switch sets. Additional sets of switches called pivot switch sets are used to accomplish this. They are added to the processors and the processor switch sets to form processor clusters. The clusters are each assigned a logical row and column location in an array. Each pivot switch set is connected to all node switch sets in the same assigned column location and to all node switch sets in the same assigned row location as the pivot set. Consequently, any two node switch sets are connected by way of a pivot set located at either (a) the intersection row of the first node set and the column of the second node set or at (b) the intersection of the column of the first node set and the row of the second node set.
摘要翻译：在诸如蝴蝶品种的大型可扩展处理器阵列中的处理器相关联的节点开关组之间的连接在节点开关组之间的行和列中被布置成像2-D网格阵列。称为枢转开关组的附加开关组用于实现这一点。它们被添加到处理器和处理器交换机集合以形成处理器集群。簇中的每一个都分配了数组中的逻辑行和列位置。每个枢轴开关组连接到相同分配列位置中的所有节点开关组，并连接到与枢轴组相同的分配行位置中的所有节点开关组。因此，任何两个节点交换机组通过位于（a）第一节点集合的交集行和第二节点集合的列的枢轴组连接，或者在（b）第一节点集合的列的交集处节点集和第二个节点集的行。

9. 发明授权

US5371733A Method and apparatus for centralized determination of virtual transmission delays in networks of counter-synchronized communication devices 失效
标题翻译：用于集中确定逆同步通信设备网络中的虚拟传输延迟的方法和装置
公开(公告)号：US5371733A
公开(公告)日：1994-12-06
申请号：US26386
申请日：1993-03-04
申请人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
发明人： Monty M. Denneau , Bruce D. Gavril , Peter H. Hochschild , Craig B. Stunkel
IPC分类号： G06F1/12 , G06F13/00 , G06F15/173 , H04J3/06 , H04L7/00 , H04Q11/04 , H04J1/16
CPC分类号： H04Q11/0421 , G06F1/12 , H04J3/0638 , H04J3/0682
摘要： For use by a particular node within a digital data communications network having a plurality of counter-synchronized nodes including the particular node, called the central service node (CSN), and at least one remote node, all nodes being clocked at a common frequency, each node being synchronized by its own nodal time counter and connected to at least one other node by at least one transmission segment that completes a transmission path from the CSN, method and apparatus for: (a) establishing any value of virtual transmission delay (vtd) at individual transmission segments; (b) non-destructively determining the existing vtd at individual transmission segments; and (c) establishing basal distributions of vtd throughout the network and determining the elements thereof, (a), (b), and (c) being achieved without the central service node knowing real transmission delay (rtd) and inter-nodal asynchrony anywhere within the network and without requiring the active participation of any remote node. Virtual transmission delay for a transmission segment is the algebraic difference between rtd and the asynchrony between its source and destination nodes. It is the fundamental parameter governing the synchronization of nodal counters and inter-nodal information transfer.
摘要翻译：为了由数字数据通信网络中的特定节点使用，该数字数据通信网络具有包括被称为中央服务节点（CSN）的特定节点，以及至少一个远程节点的多个反同步节点，所有节点以公共频率计时，每个节点由其自己的节点时间计数器同步，并通过至少一个完成来自CSN的传输路径的传输段连接到至少一个其他节点，方法和装置用于：（a）建立任何虚拟传输延迟值（vtd ）; （b）非破坏性地确定个别传输段的现有vtd; （c）在整个网络中建立vtd的基本分布并确定其元素，（a），（b）和（c）在没有中央服务节点知道实际传输延迟（rtd）和在节点间不同步的任何地方实现并且不需要任何远程节点的主动参与。传输段的虚拟传输延迟是rtd与其源节点和目的节点之间的不同步之间的代数差。它是控制节点计数器和节点间信息传输同步的基本参数。

10. 发明授权

US07619993B2 Efficient probabilistic duplicate packet detector in computer networks 失效
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US07619993B2
公开(公告)日：2009-11-17
申请号：US11264529
申请日：2005-11-01
申请人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
发明人： Carl A. Bender , Fu Chung Chang , Kevin J. Gildea , Rama J. Govindaraju , Jay R. Herring , Peter H. Hochschild , Richard A. Swetz
IPC分类号： H04L12/28 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , G08C25/00 , G06F15/16
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

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