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1. 发明授权

US07272060B1 Method, system, and circuit for performing a memory related operation 有权
标题翻译：用于执行存储器相关操作的方法，系统和电路
公开(公告)号：US07272060B1
公开(公告)日：2007-09-18
申请号：US11001940
申请日：2004-12-01
申请人： Qiang Lu , Richard Fastow , Zhigang Wang
发明人： Qiang Lu , Richard Fastow , Zhigang Wang
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/12
摘要： A method, system, and circuit for performing a memory related operation are disclosed. An operating voltage is applied to a bitline and a neighboring bitline is precharged. The precharge voltage has a magnitude less than the operating voltage. Both voltages ramp up at like or different rates. The precharge voltage can reach its effective magnitude prior to or with the operating voltage reaching its effective value.
摘要翻译：公开了一种用于执行存储器相关操作的方法，系统和电路。工作电压施加到位线，并且相邻位线被预充电。预充电电压的幅度小于工作电压。两个电压都以相同或不同的速率上升。预充电电压可以在工作电压达到其有效值之前或达到其有效幅度。

2. 发明授权

US06541338B2 Low defect density process for deep sub-0.18 &mgr;m flash memory technologies 失效
标题翻译：用于深亚0.18微米闪存技术的低缺陷密度工艺
公开(公告)号：US06541338B2
公开(公告)日：2003-04-01
申请号：US09917182
申请日：2001-07-30
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.
摘要翻译：一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。

3. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

4. 发明授权

US06852594B1 Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology 有权
标题翻译：两级源端植入，用于提高深亚0.18微米闪存技术中的源极电阻和短沟道效应
公开(公告)号：US06852594B1
公开(公告)日：2005-02-08
申请号：US10053256
申请日：2002-01-18
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of forming flash memory EEPROM devices having lightly doped source region near the critical gate region and a heavily doped source region away from the critical gate region. In a first embodiment a first source mask is formed exposing source regions and portions of the gates and implanting n dopant ions, replacing the first source mask with a second source mask that exposes a portion of the source regions and implanting n+ dopant ions. In a second embodiment a source mask is formed exposing a portion of the source regions and implanting n+ dopant ions.
摘要翻译：形成具有在临界栅极区附近的轻掺杂源极区域和远离临界栅极区域的重掺杂源极区域的快闪存储器EEPROM器件的方法。在第一实施例中，形成第一源掩模，用于暴露源极区域和栅极的部分以及注入n个掺杂剂离子，用第二源极掩模代替第一源极掩模，第二源极掩模暴露出源区域的一部分并注入n +掺杂离子。在第二实施例中，形成暴露源区的一部分并注入n +掺杂离子的源掩模。

5. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

6. 发明授权

US06754109B1 Method of programming memory cells 有权
标题翻译：编程存储单元的方法
公开(公告)号：US06754109B1
公开(公告)日：2004-06-22
申请号：US10282847
申请日：2002-10-29
申请人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
发明人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： In the present method of programming a selected flash EEPROM memory cell of a pair thereof in series, a positive voltage is applied to the drain of the selected cell to be programmed, a voltage lower than the voltage applied to the drain is applied to the source of the selected cell, a negative voltage is applied to the substrate, and a positive voltage is applied to the control gate sufficient to induce hot electron injection from the drain to the floating gate of the selected cell.
摘要翻译：在本文对串联选择的一对闪存EEPROM存储单元进行编程的方法中，将正电压施加到要被编程的选定单元的漏极，低于施加到漏极的电压的电压施加到源极，向基板施加负电压，并且将正电压施加到控制栅极，足以引起从漏极到所选电池的浮置栅极的热电子注入。

7. 发明授权

US08237210B1 Array type CAM cell for simplifying processes 有权
标题翻译：阵列型CAM单元，用于简化过程
公开(公告)号：US08237210B1
公开(公告)日：2012-08-07
申请号：US11349562
申请日：2006-02-08
申请人： Zhigang Wang , Kazuhiro Mizutani , Richard Fastow
发明人： Zhigang Wang , Kazuhiro Mizutani , Richard Fastow
IPC分类号： H01L29/76
CPC分类号： G11C15/00
摘要： A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.
摘要翻译：提出了一种包括存储单元阵列的半导体装置。存储单元以行和列排列。不相交的浅沟槽隔离区域隔离存储单元的列。还包括至少一个源极区域，其隔离在相邻的一对不相交的浅沟槽隔离区域之间并与漏极区域隔离。源极区域耦合到存储器单元阵列中的源极线。一个触点耦合选择的多个存储单元列，所述选择多个功能用作单个内容可寻址存储单元。

8. 发明授权

US06510085B1 Method of channel hot electron programming for short channel NOR flash arrays 有权
标题翻译：用于短通道NOR闪存阵列的通道热电子编程方法
公开(公告)号：US06510085B1
公开(公告)日：2003-01-21
申请号：US09861031
申请日：2001-05-18
申请人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
发明人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.
摘要翻译：编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间到存储单元的基板。

9. 发明授权

US06469939B1 Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process 有权
标题翻译：闪存器件在APDE期间提高效率（擦除后的自动程序干扰）过程
公开(公告)号：US06469939B1
公开(公告)日：2002-10-22
申请号：US09969572
申请日：2001-10-01
申请人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
发明人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.
摘要翻译：源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率闪存设备。此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极单元格已连接。

10. 发明授权

US09585550B2 Rectal expander 有权
标题翻译：直肠扩张器
公开(公告)号：US09585550B2
公开(公告)日：2017-03-07
申请号：US10561649
申请日：2004-06-24
申请人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
发明人： Eric Abel , James R. Hewit , Alan P. Slade , Zhigang Wang
IPC分类号： A61M29/00 , A61B1/32 , A61B1/31
CPC分类号： A61B1/32 , A61B1/31 , A61M29/00
摘要： There is disclosed medical apparatus of the type for use in surgery such as transanal endoscopic microsurgery, as well as methods of providing access to, inspecting and enabling surgery within a body passage. In one embodiment of the invention, medical apparatus in the form of a rectal expander (10) is disclosed, the expander (10) being adapted for location at least partly within a body passage such as the rectum (12) of a patient (14), the expander (10) having a leading end (18) and an access area in the form of an opening (20) for access from the expander (10) into the rectum (12), at least part of the opening (20) being spaced from the leading end (18), and the expander (10) being controllably movable between collapse and expansion positions, for expanding the rectum (12).
摘要翻译：公开了用于外科手术的类型的医疗装置，例如经肛门内窥镜显微外科手术，以及提供身体通道内的进入，检查和使手术的方法。在本发明的一个实施例中，公开了直肠扩张器（10）形式的医疗装置，所述扩张器（10）适于至少部分位于身体通道内，例如患者（14）的直肠（12）），所述膨胀器（10）具有前端（18）和开口（20）形式的进入区域，用于从所述膨胀器（10）进入直肠（12），所述开口（20）的至少一部分）与所述前端（18）间隔开，并且所述膨胀器（10）可控制地在塌缩和膨胀位置之间移动，用于扩张直肠（12）。

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