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1. 发明授权

US06541338B2 Low defect density process for deep sub-0.18 &mgr;m flash memory technologies 失效
标题翻译：用于深亚0.18微米闪存技术的低缺陷密度工艺
公开(公告)号：US06541338B2
公开(公告)日：2003-04-01
申请号：US09917182
申请日：2001-07-30
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.
摘要翻译：一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。

2. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

3. 发明授权

US06852594B1 Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology 有权
标题翻译：两级源端植入，用于提高深亚0.18微米闪存技术中的源极电阻和短沟道效应
公开(公告)号：US06852594B1
公开(公告)日：2005-02-08
申请号：US10053256
申请日：2002-01-18
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of forming flash memory EEPROM devices having lightly doped source region near the critical gate region and a heavily doped source region away from the critical gate region. In a first embodiment a first source mask is formed exposing source regions and portions of the gates and implanting n dopant ions, replacing the first source mask with a second source mask that exposes a portion of the source regions and implanting n+ dopant ions. In a second embodiment a source mask is formed exposing a portion of the source regions and implanting n+ dopant ions.
摘要翻译：形成具有在临界栅极区附近的轻掺杂源极区域和远离临界栅极区域的重掺杂源极区域的快闪存储器EEPROM器件的方法。在第一实施例中，形成第一源掩模，用于暴露源极区域和栅极的部分以及注入n个掺杂剂离子，用第二源极掩模代替第一源极掩模，第二源极掩模暴露出源区域的一部分并注入n +掺杂离子。在第二实施例中，形成暴露源区的一部分并注入n +掺杂离子的源掩模。

4. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

5. 发明授权

US06888157B1 N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation 有权
标题翻译： N栅极/ N基板或P栅极/ P基板电容器来表征多晶硅栅极耗尽评估
公开(公告)号：US06888157B1
公开(公告)日：2005-05-03
申请号：US09917440
申请日：2001-07-27
申请人： Zhigang Wang , Nian Yang , Yue-song He
发明人： Zhigang Wang , Nian Yang , Yue-song He
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure for characterizing polysilicon gate depletion effects of a particular semiconductor fabrication process. In one embodiment, an N-Gate/N-Substrate capacitor is fabricated with the semiconductor fabrication process which is being evaluated for its polysilicon gate depletion effects. The N-gate of capacitor structure is driven to depletion while the N-substrate is simultaneously driven to accumulation. Capacitance-voltage measurements are taken. Based on these CV measurements, the polysilicon depletion effects are then obtained for that particular semiconductor fabrication process. In another embodiment, a P-Gate/P-Substrate capacitor is fabricated with the semiconductor fabrication process. The gate of the P-Gate/P-Substrate capacitor is driven to depletion while the substrate is simultaneously driven to accumulation. Based on the CV measurements performed on the P-Gate/P-Substrate capacitor, the polysilicon depletion effects can be obtained for that particular semiconductor fabrication process. In a third embodiment, a capacitor structure device is used to evaluate the polysilicon gate depletion effects of a semiconductor fabrication process. Different voltages are selectively applied to the gate of either an N-Gate/N-Substrate capacitor or a P-Gate/P-Substrate capacitor while its capacitance is measured. Based on the CV measurements, the polysilicon gate depletion effects for that particular semiconductor fabrication process is characterized.
摘要翻译：用于表征特定半导体制造工艺的多晶硅栅极耗尽效应的电容器结构。在一个实施例中，通过正在评估其多晶硅栅极耗尽效应的半导体制造工艺来制造N栅极/ N-衬底电容器。驱动电容器结构的N栅极耗尽，同时驱动N衬底进行积累。进行电容电压测量。基于这些CV测量，然后获得针对该特定半导体制造工艺的多晶硅耗尽效应。在另一个实施例中，通过半导体制造工艺制造P栅极/ P-基板电容器。 P栅极/ P基板电容器的栅极被驱动为耗尽，同时基板同时被驱动以累积。基于在P型栅极/ P-基板电容器上执行的CV测量，可以获得针对该特定半导体制造工艺的多晶硅耗尽效应。在第三实施例中，使用电容器结构器件来评估半导体制造工艺的多晶硅栅极耗尽效应。在测量其电容时，不同的电压选择性地施加到N栅极/ N基板电容器或P栅极/ P基板电容器的栅极。基于CV测量，对该特定半导体制造工艺的多晶硅栅极耗尽效应进行了表征。

6. 发明授权

US07414281B1 Flash memory with high-K dielectric material between substrate and gate 有权
标题翻译：闪存与衬底和栅极之间的高K电介质材料
公开(公告)号：US07414281B1
公开(公告)日：2008-08-19
申请号：US10658936
申请日：2003-09-09
申请人： Richard M. Fastow , Yue-Song He , Zhigang Wang
发明人： Richard M. Fastow , Yue-Song He , Zhigang Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/513 , H01L29/7881
摘要： A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.
摘要翻译：描述闪存单元及其形成方法。闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底，栅极元件和介电层。电介质层包括介电常数大于二氧化硅的电介质材料。

7. 发明授权

US06825526B1 Structure for increasing drive current in a memory array and related method 有权
标题翻译：用于增加存储器阵列中的驱动电流的结构和相关方法
公开(公告)号：US06825526B1
公开(公告)日：2004-11-30
申请号：US10759809
申请日：2004-01-16
申请人： Yue-Song He , Nian Yang , Zhigang Wang
发明人： Yue-Song He , Nian Yang , Zhigang Wang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom. According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer and extending along the trench sidewalls and the trench bottom, where the channel region has an effective channel width, where the effective channel width increases as a height of the trench sidewalls increases.
摘要翻译：根据一个示例性实施例，存储器阵列包括位于衬底中的第一和第二隔离区域，其中第一和第二隔离区域被分离距离。存储器阵列还包括位于第一和第二隔离区之间的沟槽，其中沟槽限定衬底中的沟槽侧壁和沟底。存储器阵列还包括位于第一和第二隔离区之间的隧道氧化物层，其中隧道氧化物层位于沟槽侧壁和沟槽底部。根据该实施例，存储器阵列还包括位于隧道氧化物层下方并沿着沟槽侧壁和沟槽底部延伸的沟道区，其中沟道区具有有效沟道宽度，其中有效沟道宽度随着沟槽侧壁增加。

8. 发明授权

US06898124B1 Efficient and accurate sensing circuit and technique for low voltage flash memory devices 有权
标题翻译：高效，准确的低压闪存器件感测电路和技术
公开(公告)号：US06898124B1
公开(公告)日：2005-05-24
申请号：US10678446
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C11/56 , G11C16/06 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
摘要翻译：示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。感测电路还包括连接到第一晶体管的去耦电路。解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

9. 发明授权

US06963506B1 Circuit and technique for accurately sensing low voltage flash memory devices 有权
标题翻译：用于精确检测低压闪存器件的电路和技术
公开(公告)号：US06963506B1
公开(公告)日：2005-11-08
申请号：US10679179
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C16/06 , G11C16/26 , G11C16/30
CPC分类号： G11C16/30 , G11C16/26
摘要： An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.
摘要翻译：用于感测由目标存储器单元汲取的电流的示例性感测电路包括跨越第一节点和第二节点连接的第一晶体管，跨过第二节点连接的负载和第三节点，以及耦合到电源电压的升压电路，其中所述升压电路在所述第三节点处提供大于所述电源电压的电压。

10. 发明授权

US06617639B1 Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling 有权
标题翻译：对于ONO和隧道氧化物使用高K介电材料来改善浮栅闪存耦合
公开(公告)号：US06617639B1
公开(公告)日：2003-09-09
申请号：US10176594
申请日：2002-06-21
申请人： Zhigang Wang , Xin Guo , Yue-Song He
发明人： Zhigang Wang , Xin Guo , Yue-Song He
IPC分类号： H01L29788
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.
摘要翻译：一种浮栅闪存器件，包括：衬底，包括源极区，漏极区和位于其间的沟道区; 位于通道区域上方并通过隧道介电材料层与沟道区分离的浮栅电极; 以及控制栅电极，其位于所述浮置栅电极的上方，并且通过间隔电介质层与所述浮栅电极分离，所述互聚电介质层包括具有与所述浮栅电极相邻的底电介质材料层的修饰的ONO结构，顶介电材料层，以及包括氮化物并位于底部电介质材料层和顶部电介质材料层之间的中心层，其中隧道电介质材料层和底部电介质材料层和底部电介质材料层中的至少一个顶部介电材料层，包括高K电介质材料。

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