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1. 发明授权

US06510085B1 Method of channel hot electron programming for short channel NOR flash arrays 有权
标题翻译：用于短通道NOR闪存阵列的通道热电子编程方法
公开(公告)号：US06510085B1
公开(公告)日：2003-01-21
申请号：US09861031
申请日：2001-05-18
申请人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
发明人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.
摘要翻译：编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间到存储单元的基板。

2. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

3. 发明授权

US06996004B1 Minimization of FG-FG coupling in flash memory 有权
标题翻译：闪存中FG-FG耦合的最小化
公开(公告)号：US06996004B1
公开(公告)日：2006-02-07
申请号：US10700414
申请日：2003-11-04
申请人： Richard Fastow , Sheunghee Park
发明人： Richard Fastow , Sheunghee Park
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0416 , G11C16/0466 , G11C16/3418 , G11C16/3459
摘要： Multiple passes of the loop of program verify and programming steps are performed for minimizing the effects of FG—FG coupling during programming a flash memory device. In one embodiment of the present invention, for programming a group of at least one flash memory cell of an array, a first pass of program verify and programming steps is performed until each flash memory cell of the group attains a threshold voltage that is at least X % of a program verify level but less than the program verify level. Then, a second pass of program verify and programming steps are performed until each flash memory cell of the group attains substantially the program verify level for the threshold voltage.
摘要翻译：执行程序验证和编程步骤循环的多次通过，以在闪存设备编程期间最大限度地减少FG-FG耦合的影响。在本发明的一个实施例中，为了对一组阵列的至少一个闪存单元进行编程，执行程序验证和编程步骤的第一遍，直到该组的每个闪存单元达到至少为止的阈值电压程序的X％验证级别，但小于程序验证级别。然后，执行程序验证和编程步骤的第二遍，直到该组的每个闪速存储器单元基本上达到阈值电压的程序验证电平。

4. 发明授权

US06747900B1 Memory circuit arrangement for programming a memory cell 有权
标题翻译：用于对存储器单元进行编程的存储器电路装置
公开(公告)号：US06747900B1
公开(公告)日：2004-06-08
申请号：US10348732
申请日：2003-01-21
申请人： Sheunghee Park , Ming Sang Kwan
发明人： Sheunghee Park , Ming Sang Kwan
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0416
摘要： A memory circuit for programming a target cell is disclosed. According to one embodiment, the memory circuit comprises the target cell having a drain terminal connected to a bit line. A drain voltage is coupled to the bit line and supplies a voltage greater than a ground voltage, while a gate voltage is coupled to a gate terminal of the target cell and supplies a voltage greater the ground voltage. A source voltage is coupled to a source terminal of the target cell and supplies a voltage less than the ground voltage, and a substrate voltage is coupled to a substrate of the target cell and supplies a voltage less than the ground voltage.
摘要翻译：公开了一种用于编程目标单元的存储电路。根据一个实施例，存储器电路包括具有连接到位线的漏极端子的目标单元。漏极电压耦合到位线，并提供大于接地电压的电压，而栅极电压耦合到目标单元的栅极端子并提供大于接地电压的电压。源极电压耦合到目标单元的源极端子并且提供小于接地电压的电压，并且将衬底电压耦合到目标单元的衬底并且提供小于接地电压的电压。

5. 发明授权

US07079424B1 Methods and systems for reducing erase times in flash memory devices 有权
标题翻译：用于减少闪存设备中擦除时间的方法和系统
公开(公告)号：US07079424B1
公开(公告)日：2006-07-18
申请号：US10945914
申请日：2004-09-22
申请人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
发明人： Sungchul Lee , Sheunghee Park , Yue-Song He , Ming Sang Kwan
IPC分类号： G11C11/34
CPC分类号： G11C16/107 , G11C16/16 , G11C16/3468
摘要： A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.
摘要翻译：提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程到第一预定水平。可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

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