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1. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

2. 发明授权

US06541338B2 Low defect density process for deep sub-0.18 &mgr;m flash memory technologies 失效
标题翻译：用于深亚0.18微米闪存技术的低缺陷密度工艺
公开(公告)号：US06541338B2
公开(公告)日：2003-04-01
申请号：US09917182
申请日：2001-07-30
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.
摘要翻译：一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。

3. 发明授权

US07283398B1 Method for minimizing false detection of states in flash memory devices 有权
标题翻译：用于最小化闪速存储器件中的状态的错误检测的方法
公开(公告)号：US07283398B1
公开(公告)日：2007-10-16
申请号：US10838962
申请日：2004-05-04
申请人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
发明人： Yue-Song He , Richard Fastow , Takao Akaogi , Wing Leung , Zhigang Wang
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/344 , G11C16/3445 , G11C16/3477
摘要： The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.
摘要翻译：本发明提供一种用于确定闪存设备中的程序和擦除状态的方法。具体地，本发明的一个实施例公开了一种用于使非易失性浮动栅极存储单元的阵列中的状态的错误检测最小化的方法。多个字线被布置成多行。多个位线被布置在多个列中。该方法通过确定与一列存储器单元相关联的所选位线开始。然后，该方法通过在一个负电压下偏置一组字线来继续。字线组电耦合到相关联的存储器单元。当执行验证操作时，将负电压施加到字线组限制了来自存储器单元列中的相关联存储器单元的泄漏电流贡献。

4. 发明授权

US06852594B1 Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology 有权
标题翻译：两级源端植入，用于提高深亚0.18微米闪存技术中的源极电阻和短沟道效应
公开(公告)号：US06852594B1
公开(公告)日：2005-02-08
申请号：US10053256
申请日：2002-01-18
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of forming flash memory EEPROM devices having lightly doped source region near the critical gate region and a heavily doped source region away from the critical gate region. In a first embodiment a first source mask is formed exposing source regions and portions of the gates and implanting n dopant ions, replacing the first source mask with a second source mask that exposes a portion of the source regions and implanting n+ dopant ions. In a second embodiment a source mask is formed exposing a portion of the source regions and implanting n+ dopant ions.
摘要翻译：形成具有在临界栅极区附近的轻掺杂源极区域和远离临界栅极区域的重掺杂源极区域的快闪存储器EEPROM器件的方法。在第一实施例中，形成第一源掩模，用于暴露源极区域和栅极的部分以及注入n个掺杂剂离子，用第二源极掩模代替第一源极掩模，第二源极掩模暴露出源区域的一部分并注入n +掺杂离子。在第二实施例中，形成暴露源区的一部分并注入n +掺杂离子的源掩模。

5. 发明授权

US07151028B1 Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability 有权
标题翻译：具有等离子体生长氧化物间隔物的存储单元用于降低DIBL和Vss电阻并增加可靠性
公开(公告)号：US07151028B1
公开(公告)日：2006-12-19
申请号：US10981174
申请日：2004-11-04
申请人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
发明人： Shenqing Fang , Rinji Sugino , Kuo-Tung Chang , Zhigang Wang , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L21/26
CPC分类号： H01L29/66636 , H01L29/1037 , H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于基质。该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。

6. 发明授权

US07851306B2 Method for forming a flash memory device with straight word lines 有权
标题翻译：用于形成具有直线字线的闪速存储器件的方法
公开(公告)号：US07851306B2
公开(公告)日：2010-12-14
申请号：US12327641
申请日：2008-12-03
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

7. 发明授权

US07488657B2 Method and system for forming straight word lines in a flash memory array 有权
标题翻译：用于在闪存阵列中形成直线字线的方法和系统
公开(公告)号：US07488657B2
公开(公告)日：2009-02-10
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.
摘要翻译：本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。与漏极触点排共线的源触点的布置允许直线字线形成。

8. 发明申请

US20060286750A1 Method and system for forming straight word lines in a flash memory array 有权
公开(公告)号：US20060286750A1
公开(公告)日：2006-12-21
申请号：US11155707
申请日：2005-06-17
申请人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
发明人： Shenqing Fang , Hiroyuki Ogawa , Kuo-Tung Chang , Pavel Fastenko , Kazuhiro Mizutani , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

9. 发明授权

US08237210B1 Array type CAM cell for simplifying processes 有权
标题翻译：阵列型CAM单元，用于简化过程
公开(公告)号：US08237210B1
公开(公告)日：2012-08-07
申请号：US11349562
申请日：2006-02-08
申请人： Zhigang Wang , Kazuhiro Mizutani , Richard Fastow
发明人： Zhigang Wang , Kazuhiro Mizutani , Richard Fastow
IPC分类号： H01L29/76
CPC分类号： G11C15/00
摘要： A semiconductor apparatus is presented that includes an array of memory cells. The memory cells are arranged in rows and columns. Non-intersecting shallow trench isolation regions isolate the columns of memory cells. Also included is at least one source region that is isolated between an adjoining pair of the non-intersecting shallow trench isolation regions and isolated from a drain region. The source region is coupled to source lines in the array of memory cells. A contact couples a select plurality of the columns of memory cells, the select plurality functioning as a single content addressable memory cell.
摘要翻译：提出了一种包括存储单元阵列的半导体装置。存储单元以行和列排列。不相交的浅沟槽隔离区域隔离存储单元的列。还包括至少一个源极区域，其隔离在相邻的一对不相交的浅沟槽隔离区域之间并与漏极区域隔离。源极区域耦合到存储器单元阵列中的源极线。一个触点耦合选择的多个存储单元列，所述选择多个功能用作单个内容可寻址存储单元。

10. 发明申请

US20060035431A1 Memory cell with reduced DIBL and Vss resistance 有权
标题翻译：具有降低的DIBL和Vss电阻的存储单元
公开(公告)号：US20060035431A1
公开(公告)日：2006-02-16
申请号：US10915771
申请日：2004-08-11
申请人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
发明人： Shenqing Fang , Kuo-Tung Chang , Pavel Fastenko , Zhigang Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on substrate comprises a step of forming a spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in substrate. The method further comprises forming a high energy implant doped region adjacent to the spacer in the source region of substrate. The method further comprises forming a recess in a source region of the substrate, where the recess has a sidewall, a bottom, and a depth, and where the sidewall of the recess is situated adjacent to a source of the floating gate memory cell. According to this exemplary embodiment, the spacer causes the source to have a reduced lateral straggle and diffusion in the channel region, which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell.
摘要翻译：根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成与层叠栅极结构的源极侧壁相邻的间隔物的步骤，其中堆叠的栅极结构位于衬底中的沟道区域之上。该方法还包括在衬底的源区中形成与间隔物相邻的高能注入掺杂区。该方法还包括在衬底的源极区域中形成凹部，其中凹部具有侧壁，底部和深度，并且凹部的侧壁位于与浮动栅极存储单元的源极相邻的位置。根据该示例性实施例，间隔件导致源极在通道区域中具有减小的横向偏移和扩散，这导致浮动栅极存储单元中的漏极感应势垒降低（DIBL）的减小。

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