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1. 发明授权

US07392366B2 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches 有权
标题翻译：多线程处理器中的自适应提取门控，提取控制和控制提取的方法
公开(公告)号：US07392366B2
公开(公告)日：2008-06-24
申请号：US11228781
申请日：2005-09-16
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard J. Eickemeyer , Lee E. Eisen , Philip G. Emma , John B. Griswell , Zhigang Hu , Hung Q. Le , Douglas R. Logan , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3867
摘要： A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instruction cache fetches are skipped for any thread that is incapable of receiving fetched cache contents, e.g., because the thread is full or stalled. Also, consecutive fetches may be selected for the same thread, e.g., on a branch mis-predict. Thus, the processor avoids wasting power on unnecessary or place keeper fetches.
摘要翻译：多线程处理器，用于多线程处理器的获取控制以及在多线程处理器中获取的方法。监视处理器事件和使用（EU）符号，用于指示管道执行线程状态的下游管道条件。对于不能接收获取的高速缓存内容的任何线程，例如由于线程已满或停顿，跳过指令高速缓存提取。此外，可以针对相同的线程选择连续的提取，例如在分支误预测中。因此，处理器避免浪费电力不必要的或放置保持器提取。

2. 发明申请

US20110087865A1 Intermediate Register Mapper 失效
标题翻译：中级注册映射器
公开(公告)号：US20110087865A1
公开(公告)日：2011-04-14
申请号：US12578272
申请日：2009-10-13
申请人： Brian D. Barrick , Michael Billeci , Lee E. Eisen
发明人： Brian D. Barrick , Michael Billeci , Lee E. Eisen
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3838 , G06F9/3857
摘要： A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse.
摘要翻译：一种在寄存器重命名机制中采用中间寄存器映射器的方法，处理器和计算机程序产品。逻辑寄存器查找确定是否发生了与调度指令相关联的逻辑寄存器的命中。在这方面，逻辑寄存器查找在至少一个寄存器映射器中从一组寄存器映射器搜索，包括架构化寄存器映射器，统一主映射器和中间寄存器映射器。在一组寄存器映射器中选择对逻辑寄存器的单次命中。如果在统一主映像器中具有映射器条目的指令已经完成但尚未完成，则统一主映射器中的寄存器映射器条目的映射内容被移动到中间寄存器映射器，并且统一寄存器映射器条目被释放，因此增加可用于重用的多个统一的主映射器条目。

3. 发明授权

US07549095B1 Error detection enhancement in a microprocessor through the use of a second dependency matrix 失效
标题翻译：微处理器通过使用第二个依赖矩阵进行错误检测增强
公开(公告)号：US07549095B1
公开(公告)日：2009-06-16
申请号：US12165355
申请日：2008-06-30
申请人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
发明人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
IPC分类号： H03M13/00
CPC分类号： G06F9/3859 , G06F9/3838 , G06F9/3855 , G06F9/3861 , G06F11/0721 , G06F11/0751
摘要： A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.
摘要翻译：一种微处理器错误检测方法，包括提供主依赖矩阵，提供用于发布微操作的问题逻辑，提供包括主依赖矩阵的副本的辅依赖矩阵，提供结果可用向量，所述结果可用向量包括接收跟踪的每个依赖关系的条目，从发出逻辑发出微操作的指示，读取对应于所发出的微操作的次要依赖矩阵行，检查所读取的微操作是否依赖于跟踪依赖性通过确定从辅助依赖矩阵中读取的行中设置的任何位是否未被设置在辅助结果可用向量中，并且如果微操作被取消，则从发布逻辑接收指示。

4. 发明授权

US07769984B2 Dual-issuance of microprocessor instructions using dual dependency matrices 失效
标题翻译：使用双依赖矩阵双重发布微处理器指令
公开(公告)号：US07769984B2
公开(公告)日：2010-08-03
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

5. 发明授权

US5809323A Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor 失效
标题翻译：用于在超标量处理器的空闲执行单元内执行定点指令的方法和装置
公开(公告)号：US5809323A
公开(公告)日：1998-09-15
申请号：US530552
申请日：1995-09-19
申请人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/3836 , G06F9/384
摘要： A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution. In response to a determination that n instructions cannot be dispatched during the first processor cycle, a determination is made whether a fixed point instruction is available to be dispatched and whether dispatching the fixed point instruction to the non-FXU for execution will result in greater efficiency. In response to a determination that a fixed point instruction is not available to be dispatched or that dispatching the fixed point instruction to the non-FXU will not result in greater efficiency, dispatch of the fixed point instruction is delayed until a second processor cycle. However, in response to a determination that dispatching the fixed point instruction to the non-FXU will result in greater efficiency, the fixed point instruction is dispatched to the non-FXU and executed, thereby improving execution unit utilization.
摘要翻译：公开了一种用于在超标量处理器内执行定点指令的超标量处理器和方法。超标量处理器具有存储器和多个执行单元，包括固定点执行单元（FXU）和非固定点执行单元（非FXU）。根据本发明，从存储在存储器中的多个指令中取出要执行的一组指令。然后如果将固定点算术和逻辑指令仅发送到FXU，则可以在第一处理器周期期间将n个指令（尽可能最大数）分派到多个执行单元进行确定。如果是这样，n个指令被分派到多个执行单元执行。响应于在第一处理器周期期间不能调度n个指令的确定，确定是否可以调度固定点指令，以及是否向非FXU分派定点指令以执行将导致更高的效率。响应于确定不能发送固定点指令或者将定点指令分派到非FXU不会导致更高的效率，所以定点指令的调度被延迟到第二处理器周期。然而，响应于将定点指令发送到非FXU的确定将导致更高的效率，将定点指令分派到非FXU并执行，从而提高执行单元的利用率。

6. 发明授权

US5717587A Method and system for recording noneffective instructions within a data processing system 失效
标题翻译：在数据处理系统中记录无效指令的方法和系统
公开(公告)号：US5717587A
公开(公告)日：1998-02-10
申请号：US649753
申请日：1996-05-15
申请人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
发明人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell Adley Reininger
IPC分类号： G06F9/30 , G06F9/318 , G05B15/00
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
摘要翻译：公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

7. 发明授权

US5678016A Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization 失效
标题翻译：用于管理指令的执行的处理器和方法，所述指令确定在调度指令是否进行序列化之后
公开(公告)号：US5678016A
公开(公告)日：1997-10-14
申请号：US512741
申请日：1995-08-08
申请人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384
摘要： A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by computing the destination address within memory into which the operand of the floating-point store instruction is to be stored, thereby minimizing the delay in executing a floating-point store instruction.
摘要翻译：公开了一种用于管理包括具有多个浮点寄存器（FPR）的存储器和超标量处理器的数据处理系统内的浮点存储指令的执行的方法和装置。根据本发明，调度多个指令以供处理器执行，包括具有作为特定FPR的内容的操作数的浮点存储指令。确定特定FPR是否是用于以程序顺序在存储指令之前的第二指令的结果的目的地寄存器。如果是，则确定第二条指令是否必须在后续指令可以成功发送之前完成。响应于在成功发送后续指令之前必须完成第二条指令的确定，在完成第二条指令之后，浮点指令被取消并重新分配。响应于在成功发送后续指令之前不需要完成第二指令的确定，通过计算浮点存储指令的操作数所在的存储器内的目标地址来启动浮点存储指令的执行被存储，从而最小化执行浮点存储指令的延迟。

8. 发明授权

US5897654A Method and system for efficiently fetching from cache during a cache fill operation 失效
标题翻译：高速缓存填充操作期间从高速缓存中有效提取的方法和系统
公开(公告)号：US5897654A
公开(公告)日：1999-04-27
申请号：US881223
申请日：1997-06-24
申请人： Lee E. Eisen , Belliappa M. Kuttanna , Soummya Mallick , Rajesh B. Patel
发明人： Lee E. Eisen , Belliappa M. Kuttanna , Soummya Mallick , Rajesh B. Patel
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0862
摘要： A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.
摘要翻译：数据处理系统中的一种方法和系统，用于通过在多个数据字或指令被加载到高速缓存中允许读取器从高速缓冲存储器中读取来高效地与高速缓存存储器连接。总线接口单元请求将多个指令或数据字加载到高速缓存中。响应于由总线接口单元加载到高速缓存中的每个单独指令或数据字，存在所述多个指令或数据字中的单个指令或数据字有效的指示。一旦所需的指令或数据字具有有效的指示，则在所有指令或数据字被加载到高速缓存之前，允许提取器完成取指操作。在一个实施例中，一组无效标签位可以被用于在由总线接口单元写入高速缓存之后向读取器指示一组指令或数据字中的各个有效。

9. 发明授权

US08683180B2 Intermediate register mapper 失效
标题翻译：中间寄存器映射器
公开(公告)号：US08683180B2
公开(公告)日：2014-03-25
申请号：US12578272
申请日：2009-10-13
申请人： Brian D. Barrick , Michael Billeci , Lee E. Eisen
发明人： Brian D. Barrick , Michael Billeci , Lee E. Eisen
IPC分类号： G06F15/00
CPC分类号： G06F9/384 , G06F9/3838 , G06F9/3857
摘要： A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse.
摘要翻译：一种在寄存器重命名机制中采用中间寄存器映射器的方法，处理器和计算机程序产品。逻辑寄存器查找确定是否发生了与调度指令相关联的逻辑寄存器的命中。在这方面，逻辑寄存器查找在至少一个寄存器映射器中从一组寄存器映射器搜索，包括架构化寄存器映射器，统一主映射器和中间寄存器映射器。在一组寄存器映射器中选择对逻辑寄存器的单次命中。如果在统一主映像器中具有映射器条目的指令已经完成但尚未完成，则统一主映射器中的寄存器映射器条目的映射内容被移动到中间寄存器映射器，并且统一寄存器映射器条目被释放，因此增加可用于重用的多个统一的主映射器条目。

10. 发明申请

US20100064121A1 DUAL-ISSUANCE OF MICROPROCESSOR INSTRUCTIONS USING DUAL DEPENDENCY MATRICES 失效
标题翻译：使用双重依赖矩阵的微处理器指令的双重问题
公开(公告)号：US20100064121A1
公开(公告)日：2010-03-11
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

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