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1. 发明授权

US09069546B2 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权
标题翻译：从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行
公开(公告)号：US09069546B2
公开(公告)日：2015-06-30
申请号：US13450429
申请日：2012-04-18
申请人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/384
摘要： A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：计算机系统从当前在计数器空闲池中的多个计数器中分配特定的计数器，以计数从多个逻辑寄存器到多个物理寄存器中的特定物理寄存器的逻辑寄存器的映射的数量，响应于通过映射器单元执行指令，将至少一个逻辑寄存器从多个逻辑寄存器映射到特定物理寄存器，其中多个计数器的数量小于多个物理寄存器的数量。计算机系统响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

2. 发明申请

US20120265969A1 ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS 审中-公开
标题翻译：将计数器从计数器分配到跟踪逻辑寄存器映射到基于MAPPER的指令执行的物理寄存器
公开(公告)号：US20120265969A1
公开(公告)日：2012-10-18
申请号：US13450429
申请日：2012-04-18
申请人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
发明人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
IPC分类号： G06F9/30 , G06F9/315
CPC分类号： G06F9/30098 , G06F9/384
摘要： A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：计算机系统从当前在计数器空闲池中的多个计数器中分配特定的计数器，以计数从多个逻辑寄存器到多个物理寄存器中的特定物理寄存器的逻辑寄存器的映射的数量，响应于通过映射器单元执行指令，将至少一个逻辑寄存器从多个逻辑寄存器映射到特定物理寄存器，其中多个计数器的数量小于多个物理寄存器的数量。计算机系统响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

3. 发明授权

US07769984B2 Dual-issuance of microprocessor instructions using dual dependency matrices 失效
标题翻译：使用双依赖矩阵双重发布微处理器指令
公开(公告)号：US07769984B2
公开(公告)日：2010-08-03
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

4. 发明申请

US20100064121A1 DUAL-ISSUANCE OF MICROPROCESSOR INSTRUCTIONS USING DUAL DEPENDENCY MATRICES 失效
标题翻译：使用双重依赖矩阵的微处理器指令的双重问题
公开(公告)号：US20100064121A1
公开(公告)日：2010-03-11
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

5. 发明授权

US07013400B2 Method for managing power in a simultaneous multithread processor by loading instructions into pipeline circuit during select times based on clock signal frequency and selected power mode 有权
标题翻译：基于时钟信号频率和选择的功率模式，在选择时间内通过将指令加载到流水线电路中来管理同时多线程处理器中的电力的方法
公开(公告)号：US07013400B2
公开(公告)日：2006-03-14
申请号：US10422674
申请日：2003-04-24
申请人： Ronald N. Kalla , Minh Michelle Q. Pham , John W. Ward, III
发明人： Ronald N. Kalla , Minh Michelle Q. Pham , John W. Ward, III
IPC分类号： G06F1/32
CPC分类号： G06F9/3836 , G06F9/30189 , G06F9/3851 , G06F9/3869
摘要： A register in the control unit of the CPU that is used to keep track of the address of the current or next instruction is called a program counter. In an SMT system having two threads, the CPU has program counters for both threads and means for alternately selecting between program counters to determine which thread supplies an instruction to the instruction fetch unit (IFU). The software for the SMT assigns a priority to threads entering the code stream. Instructions from the threads are read from the instruction queues pseudo-randomly and proportional to their execution priorities in the normal power mode. If both threads have a lowest priority, a low power mode is set generating a gated select time every N clock cycles of a clock when valid instructions are loaded. N may be adjusted to vary the amount of power savings and the gated select time.
摘要翻译：用于跟踪当前或下一条指令的地址的CPU的控制单元中的寄存器称为程序计数器。在具有两个线程的SMT系统中，CPU具有用于两个线程的程序计数器和用于在程序计数器之间交替选择以确定哪个线程向指令获取单元（IFU）提供指令的装置。用于SMT的软件为输入代码流的线程分配优先级。来自线程的指令从指令队列中伪随机地读取，并与其在正常功率模式下的执行优先级成比例。如果两个线程具有最低优先级，则设置低功率模式，当加载有效指令时，每N个时钟周期产生门控选择时间。可以调节N以改变功率节省量和选通时间。

6. 发明申请

US20090217017A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY 审中-公开
标题翻译：用于最小化分支预测延迟的方法，系统和计算机程序产品
公开(公告)号：US20090217017A1
公开(公告)日：2009-08-27
申请号：US12037137
申请日：2008-02-26
申请人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
发明人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3806 , G06F9/3814
摘要： A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.
摘要翻译：提供了一种用于在流水线计算机处理环境中最小化分支预测延迟的方法，系统和计算机程序产品。该方法包括利用转移指令地址和存储在分支目标缓冲器（BTB）中的对应目标地址来检测分支回路。该方法还包括将分支循环读取到预解码指令缓冲器中，并对分支循环进行限定循环锁定。该方法还包括将形成分支循环的指令流锁定在预解码指令缓冲器中，并且处理来自缓冲器的限定分支循环指令并且断电与BTB相关联的指令获取和分支预测逻辑（BPL）。

7. 发明授权

US07549095B1 Error detection enhancement in a microprocessor through the use of a second dependency matrix 失效
标题翻译：微处理器通过使用第二个依赖矩阵进行错误检测增强
公开(公告)号：US07549095B1
公开(公告)日：2009-06-16
申请号：US12165355
申请日：2008-06-30
申请人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
发明人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
IPC分类号： H03M13/00
CPC分类号： G06F9/3859 , G06F9/3838 , G06F9/3855 , G06F9/3861 , G06F11/0721 , G06F11/0751
摘要： A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.
摘要翻译：一种微处理器错误检测方法，包括提供主依赖矩阵，提供用于发布微操作的问题逻辑，提供包括主依赖矩阵的副本的辅依赖矩阵，提供结果可用向量，所述结果可用向量包括接收跟踪的每个依赖关系的条目，从发出逻辑发出微操作的指示，读取对应于所发出的微操作的次要依赖矩阵行，检查所读取的微操作是否依赖于跟踪依赖性通过确定从辅助依赖矩阵中读取的行中设置的任何位是否未被设置在辅助结果可用向量中，并且如果微操作被取消，则从发布逻辑接收指示。

8. 发明授权

US08661230B2 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权
标题翻译：从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行
公开(公告)号：US08661230B2
公开(公告)日：2014-02-25
申请号：US13088298
申请日：2011-04-15
申请人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。计数器的数量少于物理寄存器的数量。映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

9. 发明申请

US20120265971A1 ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS 有权
标题翻译：将计数器从计数器分配到跟踪逻辑寄存器映射到基于MAPPER的指令执行的物理寄存器
公开(公告)号：US20120265971A1
公开(公告)日：2012-10-18
申请号：US13088298
申请日：2011-04-15
申请人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
发明人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
IPC分类号： G06F9/315
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。计数器的数量少于物理寄存器的数量。映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

10. 发明授权

US07822954B2 Methods, systems, and computer program products for recovering from branch prediction latency 有权
标题翻译：从分支预测延迟中恢复的方法，系统和计算机程序产品
公开(公告)号：US07822954B2
公开(公告)日：2010-10-26
申请号：US12034112
申请日：2008-02-20
申请人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/383 , G06F9/3802 , G06F9/3861
摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.
摘要翻译：分支预测算法用于生成是否采用分支的预测。取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

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