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1. 发明授权

US08468325B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

2. 发明申请

US20080133890A1 DYNAMIC RECALCULATION OF RESOURCE VECTOR AT ISSUE QUEUE FOR STEERING OF DEPENDENT INSTRUCTIONS 有权
标题翻译：发布问题动态资源向量的动态调整，用于指导相关指示
公开(公告)号：US20080133890A1
公开(公告)日：2008-06-05
申请号：US12013572
申请日：2008-01-14
申请人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
发明人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

3. 发明授权

US08082467B2 Triggering workaround capabilities based on events active in a processor pipeline 有权
标题翻译：根据处理器管道中活动的事件触发解决方法的功能
公开(公告)号：US08082467B2
公开(公告)日：2011-12-20
申请号：US12645771
申请日：2009-12-23
申请人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
摘要翻译：公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。从存储器位置获取至少一个指令。该指令被解码。与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

4. 发明申请

US20110154116A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
公开(公告)号：US20110154116A1
公开(公告)日：2011-06-23
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F11/07
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

5. 发明授权

US09298469B2 Management of multiple nested transactions 有权
标题翻译：管理多个嵌套事务
公开(公告)号：US09298469B2
公开(公告)日：2016-03-29
申请号：US13524330
申请日：2012-06-15
申请人： Fadi Y. Busaba , Brian W. Thompto
发明人： Fadi Y. Busaba , Brian W. Thompto
IPC分类号： G06F9/44 , G06F9/46 , G06F9/50 , G06F9/30 , G06F9/38
CPC分类号： G06F9/44 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Embodiments relate to implementing processor management of transactions. An aspect includes receiving an instruction from a thread. The instruction includes an instruction type, and executes within a transaction. The transaction effectively delays committing stores to memory until the transaction has completed. A processor manages transaction nesting for the instruction based on the instruction type of the instruction. The transaction nesting includes a maximum processor capacity. The transaction nesting management performs enables executing a sequence of nested transactions within a transaction, supports multiple nested transactions in a processor pipeline, or generates and maintains a set of effective controls for controlling a pipeline. The processor prevents the transaction nesting from exceeding the maximum processor capacity.
摘要翻译：实施例涉及实现事务的处理器管理。一方面包括从线程接收指令。指令包括指令类型，并在事务中执行。交易有效延迟提交存储到内存，直到交易完成。处理器根据指令的指令类型管理指令的事务嵌套。事务嵌套包括最大处理器容量。事务嵌套管理执行使得能够在事务中执行嵌套事务序列，在处理器流水线中支持多个嵌套事务，或生成并维护一组用于控制流水线的有效控制。处理器防止事务嵌套超出最大处理器容量。

6. 发明授权

US08521992B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
标题翻译：在无序微处理器中预测和避免操作与存储比较的危害
公开(公告)号：US08521992B2
公开(公告)日：2013-08-27
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

7. 发明申请

US20110153986A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
标题翻译：预期和避免操作不合格的微处理器中的操作和比较危害
公开(公告)号：US20110153986A1
公开(公告)日：2011-06-23
申请号：US12822960
申请日：2010-06-24
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/312
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
摘要翻译：一种方法和信息处理系统管理无序执行的加载和存储操作。执行加载指令和存储指令中的至少一个。确定已经遇到操作数存储比较危险。基于确定，创建操作数存储中的条目比较危险预测表。该条目至少包括已执行的指令的指令地址和与指令相关联的危险指示标志。危险指示标志表示该指令遇到操作数存储比较危险。当加载指令与危险指示标志相关联时，加载指令取决于与基本相似的标志相关联的所有存储指令。

8. 发明申请

US20130339688A1 MANAGEMENT OF MULTIPLE NESTED TRANSACTIONS 有权
标题翻译：多项交易的管理
公开(公告)号：US20130339688A1
公开(公告)日：2013-12-19
申请号：US13524330
申请日：2012-06-15
申请人： Fadi Y. Busaba , Brian W. Thompto
发明人： Fadi Y. Busaba , Brian W. Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/44 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/50 , G06F9/5011 , G06F2209/507
摘要： Embodiments relate to implementing processor management of transactions. An aspect includes receiving an instruction from a thread. The instruction includes an instruction type, and executes within a transaction. The transaction effectively delays committing stores to memory until the transaction has completed. A processor manages transaction nesting for the instruction based on the instruction type of the instruction. The transaction nesting includes a maximum processor capacity. The transaction nesting management performs enables executing a sequence of nested transactions within a transaction, supports multiple nested transactions in a processor pipeline, or generates and maintains a set of effective controls for controlling a pipeline. The processor prevents the transaction nesting from exceeding the maximum processor capacity.
摘要翻译：实施例涉及实现事务的处理器管理。一方面包括从线程接收指令。指令包括指令类型，并在事务中执行。交易有效延迟提交存储到内存，直到交易完成。处理器根据指令的指令类型管理指令的事务嵌套。事务嵌套包括最大处理器容量。事务嵌套管理执行使得能够在事务中执行嵌套事务序列，在处理器流水线中支持多个嵌套事务，或生成并维护一组用于控制流水线的有效控制。处理器防止事务嵌套超出最大处理器容量。

9. 发明申请

US20130110490A1 Verifying Processor-Sparing Functionality in a Simulation Environment 有权
标题翻译：在模拟环境中验证处理器备用功能
公开(公告)号：US20130110490A1
公开(公告)日：2013-05-02
申请号：US13285460
申请日：2011-10-31
申请人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
发明人： Stefan Letz , Joerg Deutschle , Bodo Hoppe , Erica Stuecheli , Brian W. Thompto
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F11/202 , G06F11/2242 , G06F17/5022 , G06F2217/68
摘要： A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.
摘要翻译：模拟环境验证模拟处理器内核中的处理器维护功能。仿真环境为模拟处理器核心执行第一次仿真。在仿真期间，仿真环境创建一个模拟转储文件。在稍后的时间点，仿真环境为模拟处理器核心执行第二次仿真。模拟环境节省了模拟处理器内核的状态。然后，仿真环境通过加载先前创建的仿真模型转储文件来替代模拟处理器内核的状态。然后，仿真环境将模拟处理器核心的状态设置为执行处理器备用代码，并恢复第二次仿真。

10. 发明授权

US07395414B2 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions 有权
标题翻译：动态重新计算依赖指令转向问题队列中的资源向量
公开(公告)号：US07395414B2
公开(公告)日：2008-07-01
申请号：US11056691
申请日：2005-02-11
申请人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
发明人： Hung Q. Le , Dung Q. Nguyen , Brian W. Thompto , Raymond C. Yeung
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

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