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1. 发明授权

US06157998A Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers 失效
标题翻译：用于在两个或更多个分支预测缓冲器内执行两个或多个分支指令的分支预测和分辨率的方法
公开(公告)号：US06157998A
公开(公告)日：2000-12-05
申请号：US54810
申请日：1998-04-03
申请人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
发明人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
IPC分类号： G06F9/38 , G06F15/60
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译：分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。

2. 发明授权

US5619408A Method and system for recoding noneffective instructions within a data processing system 失效
标题翻译：在数据处理系统内重新编码无效指令的方法和系统
公开(公告)号：US5619408A
公开(公告)日：1997-04-08
申请号：US387145
申请日：1995-02-10
申请人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell A. Reininger
发明人： Bryan Black , Marvin A. Denman , Lee E. Eisen , Robert T. Golla , Albert J. Loper, Jr. , Soummya Mallick , Russell A. Reininger
IPC分类号： G06F9/30 , G06F9/318 , G05B15/00
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
摘要翻译：公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

3. 发明授权

US5524224A System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing 失效
标题翻译：用于推测执行指令的系统，其中在完成分支处理之前执行错误预测的指令
公开(公告)号：US5524224A
公开(公告)日：1996-06-04
申请号：US497001
申请日：1995-06-30
申请人： Marvin A. Denman , Artie A. Pennington , Seungyoon P Song
发明人： Marvin A. Denman , Artie A. Pennington , Seungyoon P Song
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a second instruction is processed independent of information previously stored in the storage location so that the storage location is associated with the second instruction prior to completion of the branch instruction.
摘要翻译：提供了一种处理系统和操作方法，响应于分支指令，处理第一指令，使得存储位置在执行分支指令之前与第一指令相关联。响应于分支指令的执行，独立于先前存储在存储位置中的信息来处理第二指令，使得存储位置在分支指令完成之前与第二指令相关联。

4. 发明授权

US08694759B2 Generating predicted branch target address from two entries storing portions of target address based on static/dynamic indicator of branch instruction type 有权
标题翻译：基于分支指令类型的静态/动态指示符，从存储部分目标地址的两个条目生成预测分支目标地址
公开(公告)号：US08694759B2
公开(公告)日：2014-04-08
申请号：US12945732
申请日：2010-11-12
申请人： James D. Dundas , Marvin A. Denman
发明人： James D. Dundas , Marvin A. Denman
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3808
摘要： A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.
摘要翻译：提供了一种利用分支预测方案的方法和装置，其限制了功率消耗和由分支预测方案引起的消耗的面积。该方法包括访问数据结构的第一条目和第二条目，其中每个条目存储预测目标地址的一部分，使用存储在第一条目中的预测目标地址的部分确定预测目标地址，用于获取的第一类型的分支指令的获取分支指令的分支地址，以及使用存储在第一条目中的预测目标地址的部分和存储在第二条目中的预测目标地址的部分来确定预测目标地址对于第二类型的获取的分支指令。

5. 发明授权

US06477640B1 Apparatus and method for predicting multiple branches and performing out-of-order branch resolution 失效
标题翻译：用于预测多个分支并执行无序分支分辨率的装置和方法
公开(公告)号：US06477640B1
公开(公告)日：2002-11-05
申请号：US09659401
申请日：2000-09-11
申请人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
发明人： Jeffrey Pidge Rupley, II , Marvin A. Denman , Bradley G. Burgess , David C. Holloway
IPC分类号： G06F1560
CPC分类号： G06F9/3851 , G06F9/3844 , G06F9/3861
摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.
摘要翻译：分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。

6. 发明授权

US4893268A Circuit and method for accumulating partial products of a single, double or mixed precision multiplication 失效
标题翻译：用于积累单，双或混合精度乘积的部分乘积的电路和方法
公开(公告)号：US4893268A
公开(公告)日：1990-01-09
申请号：US181865
申请日：1988-04-15
申请人： Marvin A. Denman, Jr. , John M. Young , Mitch K. Alsup
发明人： Marvin A. Denman, Jr. , John M. Young , Mitch K. Alsup
IPC分类号： G06F7/52
CPC分类号： G06F7/5275 , G06F2207/3816 , G06F7/49952
摘要： A circuit for use in conjunction with a multiplier receives a portion of completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand. The circuit is adaptable for use with input operands having single or double precision data formats. The accumulation time required depends upon which data format mode the circuit is operating in.
摘要翻译：与乘法器一起使用的电路接收完成的产品位的一部分，以及累加的一部分和和进位，提供完整的输出产物操作数。该电路适用于具有单精度或双精度数据格式的输入操作数。所需的累积时间取决于电路正在运行的数据格式模式。

7. 发明授权

US5613081A Method of operating a data processor with rapid address comparison for data forwarding 失效
标题翻译：用于数据转发的快速地址比较操作数据处理器的方法
公开(公告)号：US5613081A
公开(公告)日：1997-03-18
申请号：US526398
申请日：1995-09-11
申请人： Bryan P. Black , Marvin A. Denman
发明人： Bryan P. Black , Marvin A. Denman
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3802 , G06F12/0859
摘要： A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.
摘要翻译：数据处理器（10）具有用于产生每个请求数据双字的地址的执行单元（18,20）。数据处理器在数据处理器的存储器高速缓存中未找到所请求的双字时，提取整个存储器行，四个双字数据，其中包含所请求的双字。当从外部存储器系统返回时，数据处理器最终将所请求的数据存储在存储器高速缓存（40）中。数据处理器还具有用于在某些情况下将先前请求的双字直接转发到执行单元的转发电路（48,50）。如果数据处理器自上次存储器高速缓存未命中以来没有超过存储器线边界，并且所请求和接收的双字的两个最低有效位逻辑上匹配，转发电路将转发所请求的双字。

8. 发明授权

US5493669A Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits 失效
标题翻译：用于同时搜索重命名缓冲器的两个字段的数据处理器，其具有第一和第二最近的同步位
公开(公告)号：US5493669A
公开(公告)日：1996-02-20
申请号：US25453
申请日：1993-03-03
申请人： Marvin A. Denman, Jr.
发明人： Marvin A. Denman, Jr.
IPC分类号： G06F9/38 , G06F9/32 , G06F9/42
CPC分类号： G06F9/30061 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： A data processor has a plurality of execution units (12), a rename buffer (14) coupled to at least one of the execution units and a plurality of architectural registers (16) coupled to at least one execution unit and to the rename buffer. The rename buffer periodically receives and stores the result and periodically receives requests for the operand. Each received result and operand is associated with an architectural register. The rename buffer periodically forwards one of a set of received results to an execution unit. Each received result of the set is associated with the same architectural register. The rename buffer is operable to determine which entry is the most recently allocated among several that will update the same architectural register. This ability to both manage results destined for the same architectural register and to forward only the appropriate value increases data processor throughput and reduces instruction stalls.
摘要翻译：数据处理器具有多个执行单元（12），耦合到至少一个执行单元的重命名缓冲器（14）和耦合到至少一个执行单元和重命名缓冲器的多个架构寄存器（16）。重命名缓冲区周期性地接收并存储结果并周期性地接收对操作数的请求。每个接收到的结果和操作数与架构寄存器相关联。重命名缓冲器周期性地将一组接收结果中的一个转发到执行单元。该集合的每个接收结果与相同的架构寄存器相关联。重命名缓冲区可操作以确定哪些条目是最近在几个将更新相同架构寄存器之间分配的条目。这种管理结果的能力同样适用于同一架构寄存器，并仅转发适当的值可以提高数据处理器吞吐量并减少指令停顿。

9. 发明授权

US4903264A Method and apparatus for handling out of order exceptions in a pipelined data unit 失效
标题翻译：用于处理流水线数据单元中的异常异常的方法和装置
公开(公告)号：US4903264A
公开(公告)日：1990-02-20
申请号：US182551
申请日：1988-04-18
申请人： Yoav Talgam , Mitch K. Alsup , Marvin A. Denman
发明人： Yoav Talgam , Mitch K. Alsup , Marvin A. Denman
IPC分类号： G06F7/48 , G06F9/38 , G06F11/14
CPC分类号： G06F7/48 , G06F11/1441 , G06F9/3863 , G06F7/49905
摘要： A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.
摘要翻译：一种用于数据处理器的流水线数据单元，该数据单元具有特殊的输入操作数检查逻辑，用于在任何一个或两个输入操作数失败时输出精确的异常处理机制，并输出结果格式逻辑以使不精确的异常处理如果输出结果不能以选定的格式提供，那么机制。还提供特殊缓冲器以允许每个指令独有的控制和状态信息与该指令一起流经管道。与数据单元中正在执行的每个指令相关的足够信息被保留并且使处理程序容易获得，从而如果可以恢复，则可以处理每种类型的异常。

10. 发明申请

US20120124347A1 BRANCH PREDICTION SCHEME UTILIZING PARTIAL-SIZED TARGETS 有权
标题翻译：分支预测方案利用部分大小的目标
公开(公告)号：US20120124347A1
公开(公告)日：2012-05-17
申请号：US12945732
申请日：2010-11-12
申请人： James D. Dundas , Marvin A. Denman
发明人： James D. Dundas , Marvin A. Denman
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3808
摘要： A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.
摘要翻译：提供了一种利用分支预测方案的方法和装置，其限制了功率消耗和由分支预测方案引起的消耗的面积。该方法包括访问数据结构的第一条目和第二条目，其中每个条目存储预测目标地址的一部分，使用存储在第一条目中的预测目标地址的部分确定预测目标地址，用于获取的第一类型的分支指令的获取分支指令的分支地址，以及使用存储在第一条目中的预测目标地址的部分和存储在第二条目中的预测目标地址的部分来确定预测目标地址对于第二类型的获取的分支指令。

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