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1. 发明授权

US07769984B2 Dual-issuance of microprocessor instructions using dual dependency matrices 失效
标题翻译：使用双依赖矩阵双重发布微处理器指令
公开(公告)号：US07769984B2
公开(公告)日：2010-08-03
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

2. 发明申请

US20100064121A1 DUAL-ISSUANCE OF MICROPROCESSOR INSTRUCTIONS USING DUAL DEPENDENCY MATRICES 失效
标题翻译：使用双重依赖矩阵的微处理器指令的双重问题
公开(公告)号：US20100064121A1
公开(公告)日：2010-03-11
申请号：US12208683
申请日：2008-09-11
申请人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , Lee E. Eisen , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译：解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。

3. 发明授权

US09069546B2 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权
标题翻译：从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行
公开(公告)号：US09069546B2
公开(公告)日：2015-06-30
申请号：US13450429
申请日：2012-04-18
申请人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/384
摘要： A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：计算机系统从当前在计数器空闲池中的多个计数器中分配特定的计数器，以计数从多个逻辑寄存器到多个物理寄存器中的特定物理寄存器的逻辑寄存器的映射的数量，响应于通过映射器单元执行指令，将至少一个逻辑寄存器从多个逻辑寄存器映射到特定物理寄存器，其中多个计数器的数量小于多个物理寄存器的数量。计算机系统响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

4. 发明授权

US08661230B2 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权
标题翻译：从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行
公开(公告)号：US08661230B2
公开(公告)日：2014-02-25
申请号：US13088298
申请日：2011-04-15
申请人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。计数器的数量少于物理寄存器的数量。映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

5. 发明授权

US07549095B1 Error detection enhancement in a microprocessor through the use of a second dependency matrix 失效
标题翻译：微处理器通过使用第二个依赖矩阵进行错误检测增强
公开(公告)号：US07549095B1
公开(公告)日：2009-06-16
申请号：US12165355
申请日：2008-06-30
申请人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
发明人： Gregory W. Alexander , Lee E. Eisen , Brian W. Thompto , John W. Ward, III
IPC分类号： H03M13/00
CPC分类号： G06F9/3859 , G06F9/3838 , G06F9/3855 , G06F9/3861 , G06F11/0721 , G06F11/0751
摘要： A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.
摘要翻译：一种微处理器错误检测方法，包括提供主依赖矩阵，提供用于发布微操作的问题逻辑，提供包括主依赖矩阵的副本的辅依赖矩阵，提供结果可用向量，所述结果可用向量包括接收跟踪的每个依赖关系的条目，从发出逻辑发出微操作的指示，读取对应于所发出的微操作的次要依赖矩阵行，检查所读取的微操作是否依赖于跟踪依赖性通过确定从辅助依赖矩阵中读取的行中设置的任何位是否未被设置在辅助结果可用向量中，并且如果微操作被取消，则从发布逻辑接收指示。

6. 发明授权

US09075600B2 Program status word dependency handling in an out of order microprocessor design 有权
标题翻译：程序状态字依赖处理在一个无序的微处理器设计
公开(公告)号：US09075600B2
公开(公告)日：2015-07-07
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

7. 发明申请

US20130339666A1 SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION 审中-公开
公开(公告)号：US20130339666A1
公开(公告)日：2013-12-19
申请号：US13524471
申请日：2012-06-15
申请人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
发明人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/3017 , G06F9/384
摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.

8. 发明申请

US20110320782A1 PROGRAM STATUS WORD DEPENDENCY HANDLING IN AN OUT OF ORDER MICROPROCESSOR DESIGN 有权
标题翻译：程序状态字依赖于处理订单微处理器设计
公开(公告)号：US20110320782A1
公开(公告)日：2011-12-29
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译：一种处理计算机程序指令的计算机实现方法。该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。

9. 发明授权

US08751747B2 Management of cache replacement status in cache memory 有权
标题翻译：管理高速缓存中缓存替换状态
公开(公告)号：US08751747B2
公开(公告)日：2014-06-10
申请号：US12037829
申请日：2008-02-26
申请人： Robert J. Sonnelitter, III , Gregory W. Alexander , Brian R. Prasky
发明人： Robert J. Sonnelitter, III , Gregory W. Alexander , Brian R. Prasky
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/121
摘要： A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch reference tag to a previous instruction fetch reference tag, maintaining a cache replacement status of the cache line if the instruction fetch reference tag is the same as the previous instruction fetch reference tag, and upgrading the cache replacement status of the cache line if the instruction fetch reference tag is different from the previous instruction fetch reference tag, whereby the cache replacement status of the cache line is upgraded if the instruction stream is independently fetched more than once. A corresponding system and computer program product.
摘要翻译：一种用于管理高速缓存存储器的方法，包括接收高速缓冲存储器中的指令流的指令取出，其中指令获取包括用于指令流的指令获取参考标签，并且指令流至少部分地包括在高速缓存行内，指令获取参考标签到先前的指令获取参考标签，如果指令获取引用标签与先前的指令获取引用标签相同，则保持高速缓存行的高速缓存替换状态，并且如果高速缓存行的高速缓存替换状态指令获取参考标签与先前的指令获取参考标签不同，从而如果指令流被独立地提取多次，则缓存行的高速缓存替换状态被升级。相应的系统和计算机程序产品。

10. 发明申请

US20110154298A1 COLLECTING COMPUTER PROCESSOR INSTRUMENTATION DATA 失效
标题翻译：收集计算机处理器仪表数据
公开(公告)号：US20110154298A1
公开(公告)日：2011-06-23
申请号：US12645687
申请日：2009-12-23
申请人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
发明人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409
摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.
摘要翻译：一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。全局完成表中的一个指令组被标记为标记组。存储用于与标记组相关联的处理阶段处理指令的仪表数据。采样信号脉冲触发确定标记的组是否是下一个完成指令组。当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。

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