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1. 发明授权

US06518185B1 Integration scheme for non-feature-size dependent cu-alloy introduction 有权
标题翻译：非特征尺寸依赖的Cu合金介绍的集成方案
公开(公告)号：US06518185B1
公开(公告)日：2003-02-11
申请号：US10127521
申请日：2002-04-22
申请人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
发明人： Pin-Chin Connie Wang , Fei Wang , Kashmir Sahota , Steven Avanzino , Amit Marathe , Matthew Buynoski , Ercan Adem , Christy Woo
IPC分类号： H01L2144
CPC分类号： H01L21/76877
摘要： In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.
摘要翻译：在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。进行退火步骤以将掺杂元素扩散到开口中的铜中。

2. 发明授权

US06433402B1 Selective copper alloy deposition 有权
标题翻译：选择性铜合金沉积
公开(公告)号：US06433402B1
公开(公告)日：2002-08-13
申请号：US09713314
申请日：2000-11-16
申请人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit Marathe , Diana M. Schonauer
发明人： Christy Mei-Chu Woo , Pin-Chin Connie Wang , Amit Marathe , Diana M. Schonauer
IPC分类号： H01L2900
CPC分类号： H01L21/76849 , H01L21/76843 , H01L21/76867 , H01L21/76877
摘要： Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider openings, thereby improving electromigration resistance without increasing narrow line resistance. Embodiments include annealing after filling the relatively narrow openings and before filling the relatively wider openings, thereby reducing void formation in narrow lines.
摘要翻译：最初沉积铜或低电阻率铜合金以填充相对窄的开口，留下未填充的较宽的开口。然后选择性地沉积具有相对于铜具有改善的电迁移阻力的铜合金以填充相对较宽的开口，由此在不增加窄线电阻的情况下提高电迁移阻力。实施例包括在填充相对窄的开口之后并且在填充相对较宽的开口之前的退火，从而减少窄线中的空隙形成。

3. 发明申请

US20050224979A1 CU INTERCONNECTS WITH COMPOSITE BARRIER LAYERS FOR WAFER-TO-WAFER UNIFORMITY 有权
标题翻译：具有复合阻挡层的CU互连用于波形到波长均匀性
公开(公告)号：US20050224979A1
公开(公告)日：2005-10-13
申请号：US10811860
申请日：2004-03-30
申请人： Amit Marathe , Connie Wang , Christy Woo
发明人： Amit Marathe , Connie Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846
摘要： A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous α-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of α-Ta, e.g., as at a thickness of bout 50 Å to about 100 Å. Embodiments include composite barrier layers having a thickness ratio of α-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.
摘要翻译：在Cu互连中形成复合α-Ta /分级氮化钽/ TaN阻挡层，其具有为提高晶片到晶片的均匀性，电迁移电阻和可靠性，降低的接触电阻和增加的工艺裕度而设计的结构。实施例包括在包含Cu的低k层间电介质中的双镶嵌结构和在低k材料上包含TaN的初始层的复合势垒层，初始TaN层上的氮化钽梯度层和连续的α-Ta 层叠在梯度氮化钽层上。实施方案包括以足以确保α-Ta沉积的厚度形成初始TaN层，例如在50至大约的厚度。实施例包括厚度比为α-Ta和梯度氮化钽的复合阻挡层：初始TaN为约2.5:1至约3.5:1，以提高电迁移阻力和晶片与晶片的均匀性。

4. 发明授权

US07155359B1 Determination of device failure characteristic 失效
标题翻译：设备故障特性的确定
公开(公告)号：US07155359B1
公开(公告)日：2006-12-26
申请号：US10884208
申请日：2004-07-02
申请人： Hyeon-Seag Kim , Amit Marathe , Kurt Taylor
发明人： Hyeon-Seag Kim , Amit Marathe , Kurt Taylor
IPC分类号： G06F15/00
CPC分类号： G01R31/2621 , G01R31/2642 , G01R31/287
摘要： For determining a failure characteristic of a semiconductor device, a leakage current characteristic is measured for the semiconductor device to determine a plurality of stress bias zones. A respective set of parameters that define a respective failure characteristic of the semiconductor device is determined for each of the stress bias zones such that the failure characteristic is accurately determined for a wide range of operating voltages.
摘要翻译：为了确定半导体器件的故障特性，测量半导体器件的漏电流特性以确定多个应力偏置区。针对每个应力偏置区域确定限定半导体器件的相应故障特性的相应参数集，使得针对宽范围的工作电压精确地确定故障特性。

5. 发明授权

US06309959B1 Formation of self-aligned passivation for interconnect to minimize electromigration 有权
标题翻译：形成用于互连的自对准钝化，以最小化电迁移
公开(公告)号：US06309959B1
公开(公告)日：2001-10-30
申请号：US09630943
申请日：2000-08-03
申请人： Pin-Chin C. Wang , Lu You , Joffre Bernard , Amit Marathe
发明人： Pin-Chin C. Wang , Lu You , Joffre Bernard , Amit Marathe
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L21/76888
摘要： An interconnect opening of an integrated circuit is filled with a conductive fill with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first conductive material is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The interconnect opening is further filled with a second conductive material by growing the second conductive material from the seed layer to form a conductive fill of the first conductive material and the second conductive material within the interconnect opening. The first conductive material and the second conductive material are comprised of a bulk metal, and at least one of the first conductive material and the second conductive material is a metal alloy having an alloy dopant in the bulk metal. In addition, a plasma treatment process is performed to remove any metal oxide or metal hydroxide from a top surface of the conductive fill. A self-aligned passivation material of an intermetallic compound or a metal oxide is formed at the top surface of the conductive fill with the alloy dopant that segregates out and to the top surface of the conductive fill. The intermetallic compound or the metal oxide is an additional passivation material between the top surface of the conductive fill and a layer of bulk passivation material deposited over the semiconductor wafer to prevent drift of the bulk metal, such as copper, of the conductive fill along a bottom surface of the layer of bulk passivation material.
摘要翻译：集成电路的互连开口填充有导电填料，其中互连开口位于半导体晶片上的绝缘层内。第一导电材料的籽晶层保形地沉积在互连开口的侧壁和底壁上。通过从种子层生长第二导电材料以形成互连开口内的第一导电材料和第二导电材料的导电填料，互连开口进一步填充有第二导电材料。第一导电材料和第二导电材料由体金属组成，并且第一导电材料和第二导电材料中的至少一个是在本体金属中具有合金掺杂剂的金属合金。此外，进行等离子体处理工艺以从导电填料的顶表面去除任何金属氧化物或金属氢氧化物。在导电填料的顶表面上形成金属间化合物或金属氧化物的自对准钝化材料，其中合金掺杂剂分离出导电填料的顶表面。金属间化合物或金属氧化物是在导电填料的顶表面和沉积在半导体晶片上的体积钝化材料层之间的另外的钝化材料，以防止导电填料的体金属（例如铜）沿着底部表面堆积钝化材料层。

6. 发明授权

US07755194B1 Composite barrier layers with controlled copper interface surface roughness 有权
标题翻译：具有受控铜界面表面粗糙度的复合阻挡层
公开(公告)号：US07755194B1
公开(公告)日：2010-07-13
申请号：US11376190
申请日：2006-03-16
申请人： Amit Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo , Paul L. King
发明人： Amit Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo , Paul L. King
IPC分类号： H01L23/495 , H01L29/40
CPC分类号： H01L23/5329 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an α-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 Å to about 50 Å. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the N2 flow rate and/or ratio of the thickness of the combined α-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.
摘要翻译：在具有受控表面粗糙度的Cu互连件中形成复合α-Ta /梯度氮化钽/ TaN阻挡层，以提高粘合性，电迁移性和可靠性。实施例包括在初始TaN层上衬有镶嵌开口，例如在低k层间电介质中的双镶嵌开口，具有初始TaN层，然后在分级上形成α-Ta层 TaN层，所述复合阻挡层的平均表面粗糙度（Ra）为约至约为50埃。实施例还包括通过改变组合的α-Ta和梯度氮化钽层的厚度的N2流率和/或比率与初始TaN层的厚度来控制复合阻挡层的表面粗糙度。

7. 发明授权

US07340360B1 Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness 有权
标题翻译：通过氧化物厚度的缩放来确定具有应力电压窗分析延伸的半导体器件的投射寿命的方法
公开(公告)号：US07340360B1
公开(公告)日：2008-03-04
申请号：US11349076
申请日：2006-02-08
申请人： John Zhang , Kurt Taylor , Eugene Zhao , Amit Marathe , Rolf Geilenkeuser , Joerg-Oliver Weidner
发明人： John Zhang , Kurt Taylor , Eugene Zhao , Amit Marathe , Rolf Geilenkeuser , Joerg-Oliver Weidner
IPC分类号： G06F19/00
CPC分类号： G01R31/2848
摘要： A method for efficiently and accurately measuring a maximum Vcc calculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vce extraction.
摘要翻译：用于有效和准确地测量微处理器和其他半导体产品的最大V cc计算或故障率和寿命投影的方法分析地将施加于较薄氧化物的低电压缩放为较厚的氧化物。从而获得更接近使用电压的扩展电压窗，从而提供精确的电压加速因子和最大提取。

8. 发明授权

US07033940B1 Method of forming composite barrier layers with controlled copper interface surface roughness 有权
标题翻译：形成具有受控铜界面表面粗糙度的复合阻挡层的方法
公开(公告)号：US07033940B1
公开(公告)日：2006-04-25
申请号：US10811866
申请日：2004-03-30
申请人： Amit Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo , Paul L. King
发明人： Amit Marathe , Connie Pin-Chin Wang , Christy Mei-Chu Woo , Paul L. King
IPC分类号： H01L21/44
CPC分类号： H01L23/5329 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an α-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 Å to about 50 Å. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the N2 flow rate and/or ratio of the thickness of the combined α-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.
摘要翻译：在具有受控表面粗糙度的Cu互连件中形成复合α-Ta /梯度氮化钽/ TaN阻挡层，以提高粘附性，电迁移性和可靠性。实施例包括在初始TaN层上衬有镶嵌开口，例如在低k层间电介质中的双镶嵌开口，并具有初始TaN层，然后在渐变层上形成α-Ta层 TaN层，所述复合阻挡层的平均表面粗糙度（Ra）为约至约为50。实施例还包括通过改变N 2 N 2流速和/或组合的α-Ta和梯度氮化钽层的厚度与初始的氮化钽层的厚度的比率来控制复合阻挡层的表面粗糙度 TaN层。

9. 发明授权

US07415461B1 Apparatus and method for merging results of approximate matching operations 有权
标题翻译：用于合并近似匹配操作结果的装置和方法
公开(公告)号：US07415461B1
公开(公告)日：2008-08-19
申请号：US11195888
申请日：2005-08-03
申请人： Sudipto Guha , Nikolas Koudas , Amit Marathe , Divesh Srivastava
发明人： Sudipto Guha , Nikolas Koudas , Amit Marathe , Divesh Srivastava
IPC分类号： G06F7/00
CPC分类号： G06F17/30696 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99937
摘要： A device and a method are provided. Approximate match operations are performed for each of a group of attributes for each of a group of tuples with respect to a query to create a respective ranking for each of the group of attributes. The rankings of the group of attributes are combined to provide a ranking score for each of the group of tuples. Data representing a ranking score of each of the group of tuples is generated according to a position of a respective ranking of each one of the group of tuples for a first k positions of the ranking. K of top ranked ones of the group of tuples are identified based at least in part on the generated data, wherein a number of the group of tuples is n and k
摘要翻译：提供了一种设备和方法。对于关于查询的一组元组中的每一个的一组属性中的每一个执行近似匹配操作，以为该属性组中的每一个创建相应的排名。组合属性的排名被组合以提供每组元组的排名得分。根据排序的第一k个位置的组元组中的每一个的相应排名的位置来生成表示每组元组的排名得分的数据。至少部分地基于所生成的数据来识别组元组中的顶级排名的K，其中该组元组的数目为n且k

10. 发明授权

US07026225B1 Semiconductor component and method for precluding stress-induced void formation in the semiconductor component 有权
标题翻译：用于排除半导体部件中的应力诱导的空隙形成的半导体部件和方法
公开(公告)号：US07026225B1
公开(公告)日：2006-04-11
申请号：US10697214
申请日：2003-10-29
申请人： Christine Hau-Riege , Amit Marathe , John Sanchez, Jr.
发明人： Christine Hau-Riege , Amit Marathe , John Sanchez, Jr.
IPC分类号： H01L21/4163 , H01L21/326 , H01L21/479
CPC分类号： H01L21/76838 , H01L23/528 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.
摘要翻译：具有适合于抑制应力诱导的空隙形成的特征的半导体部件和半导体部件的制造方法。提供具有主表面的半导体衬底。在主表面上形成介电材料层。在电介质材料层上形成金属化系统，其中金属化系统包括具有间隙或孔的部分，其抑制应力诱导的空隙形成。

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