专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070284748A1 Copper interconnects with improved electromigration lifetime 有权
标题翻译：铜互连具有改善的电迁移寿命
公开(公告)号：US20070284748A1
公开(公告)日：2007-12-13
申请号：US11448788
申请日：2006-06-08
申请人： Christy Woo , Jun "Charlie" Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
发明人： Christy Woo , Jun "Charlie" Zhai , Paul Besser , Kok-Yong Yiang , Richard C. Blish , Christine Hau-Riege
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.
摘要翻译：通过图案化之后Cu线和其上的覆盖层之间的剥离应力通过改变通孔的形状并定位通孔来减小，以增加通孔和线边缘之间的空间，从而增加电迁移寿命。实施例包括改变通孔的形状，如通过形成椭圆形或矩形形状的通孔，使得椭圆形的短轴与线之间的比例或矩形的宽度与线宽的比率小于约0.7。

2. 发明授权

US06768323B1 System and method for determining location of extrusion in interconnect 失效
标题翻译：用于确定互连中挤出位置的系统和方法
公开(公告)号：US06768323B1
公开(公告)日：2004-07-27
申请号：US10283463
申请日：2002-10-30
申请人： Christine Hau-Riege , Stefan Hau-Riege
发明人： Christine Hau-Riege , Stefan Hau-Riege
IPC分类号： G01R3126
CPC分类号： G01R31/2853
摘要： For locating an extrusion from an interconnect, an extrusion monitor structure is formed to surround the interconnect and is separated from the interconnect by a dielectric material. A first via is coupled to the interconnect, and a second via is coupled to the extrusion monitor structure and separated from the first via by a via distance (Lv). The extrusion is located at an extrusion site distance (Lextrusion) from the first via and between the first and second vias to short-circuit the interconnect to the extrusion monitor structure. A resistance (Rtotal) between the first and second vias is measured, and the Lextrusion is determined from a relationship with Rtotal, Lv, and resistivities and dimensions of the interconnect and the extrusion monitor structure.
摘要翻译：为了从互连件定位挤出物，形成挤出监测器结构以围绕互连并通过介电材料与互连件分离。第一通孔耦合到互连，并且第二通孔耦合到挤出监控器结构，并且与第一通孔相隔一个通孔距离（Lv）。挤出位于第一通孔和第一和第二通孔之间的挤出位置距离（拉挤）处，以将互连件短路到挤出监测器结构。测量第一和第二通孔之间的电阻（Rtotal），并且根据互连和挤出监测器结构的Rtotal，Lv以及电阻率和尺寸的关系确定Lextrusion。

3. 发明授权

US07153774B2 Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability 有权
标题翻译：制造具有铜镶嵌的具有增强的电迁移可靠性的半导体器件的方法
公开(公告)号：US07153774B2
公开(公告)日：2006-12-26
申请号：US10165679
申请日：2002-06-06
申请人： Stefan Hau-Riege , Christine Hau-Riege , Wen-Yue Zheng
发明人： Stefan Hau-Riege , Christine Hau-Riege , Wen-Yue Zheng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76858
摘要： A method of making a semiconductor device is described. That method includes forming a copper containing layer on a substrate, and forming an alloying layer that includes an alloying element on the copper containing layer. After applying heat to cause an intermetallic layer that includes copper and the alloying element to form on the surface of the copper containing layer, a barrier layer is formed on the intermetallic layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在基板上形成含铜层，并且在含铜层上形成包含合金元素的合金化层。在加热之后，在含铜层的表面上形成包含铜和合金元素的金属间层，在金属间层上形成阻挡层。

4. 发明申请

US20070278484A1 METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS CAUSED BY POROUS BARRIER MATERIALS 审中-公开
标题翻译：估计多孔障碍物材料引起的电化学效应的方法与试验结构
公开(公告)号：US20070278484A1
公开(公告)日：2007-12-06
申请号：US11626705
申请日：2007-01-24
申请人： Frank Feustel , Christine Hau-Riege , Tobias Letz
发明人： Frank Feustel , Christine Hau-Riege , Tobias Letz
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： By providing a test structure for electromigration tests in semiconductor devices, which may indicate the status of a barrier layer at the bottom of a test via in the structure, a significantly increased reliability of respective electromigration tests may be obtained. Furthermore, the degree of porosity of the barrier layer may be estimated on the basis of the resulting test structure, which comprises a feed line having an increased probability for void formation compared to the test via, when a specific degree of porosity is created in the test via.
摘要翻译：通过提供用于半导体器件中的电迁移测试的测试结构，其可以指示在结构中的测试通孔底部的阻挡层的状态，可以获得相应的电迁移测试的显着提高的可靠性。此外，可以基于所得到的测试结构来估计阻挡层的孔隙率，该测试结构包括与测试孔相比具有增加的空隙形成概率的进料线，当在通过测试。

5. 发明授权

US06870262B2 Wafer-bonding using solder and method of making the same 有权
标题翻译：使用焊料的晶圆焊接及其制造方法
公开(公告)号：US06870262B2
公开(公告)日：2005-03-22
申请号：US10672152
申请日：2003-09-25
申请人： Stefan Hau-Riege , Christine Hau-Riege
发明人： Stefan Hau-Riege , Christine Hau-Riege
IPC分类号： H01L21/301 , H01L21/98 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/50 , H01L2224/05001 , H01L2224/16
摘要： A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.
摘要翻译：提供了一种用于形成晶片叠层的方法。这可以包括在第一晶片的表面上提供具有第一多个金属化沟槽的第一晶片。可以提供第二晶片，其具有在面向第一晶片的第二晶片的表面上的第二多个金属化沟槽。第一多个金属化沟槽可以焊接到第二多个金属化沟槽。

6. 发明授权

US06822473B1 Determination of permeability of layer material within interconnect 失效
标题翻译：互连中层材料的渗透性的测定
公开(公告)号：US06822473B1
公开(公告)日：2004-11-23
申请号：US10283447
申请日：2002-10-30
申请人： Christine Hau-Riege , Stefan Hau-Riege , Amit P. Marathe
发明人： Christine Hau-Riege , Stefan Hau-Riege , Amit P. Marathe
IPC分类号： G01R27/26 , G01R31/28 , H01L23/544
CPC分类号： H01L22/34 , G01R27/26 , G01R31/2884 , G01R31/2894
摘要： Electromigration permeability is determined for a layer material within an interconnect test structure comprised of a feeder line, a test line, and a supply line. A no-flux structure is disposed between the feeder line and the test line, and the layer material is disposed between the test line and the supply line. A respective current density and length product for each of the test line and the supply line is less than a critical Blech length constant, (J*L)CRIT. A net current density and length product (J*L)NET for the test line and the supply line is greater than the (J*L)CRIT. The electromigration permeability of the layer material is determined from an electromigration lifetime of the interconnect test structure with current flowing therein.
摘要翻译：在由馈电线，测试线和供电线构成的互连测试结构内的层材料确定电迁移渗透性。在馈电线和测试线之间设置无助焊剂结构，并且层材料设置在测试线和供电线之间。测试线和供应线各自的电流密度和长度乘积小于临界Blech长度常数（J * L）CRIT。测试线和供电线的净电流密度和长度乘积（J * L）NET大于（J * L）CRIT。层材料的电迁移渗透率由互连测试结构的电流迁移寿命确定，其中电流流过其中。

7. 发明申请

US20070300200A1 Integrated circuit design system 有权
标题翻译：集成电路设计系统
公开(公告)号：US20070300200A1
公开(公告)日：2007-12-27
申请号：US11475675
申请日：2006-06-26
申请人： Christine Hau-Riege , Amit P. Marathe
发明人： Christine Hau-Riege , Amit P. Marathe
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.
摘要翻译：本发明提供了一种集成电路设计系统，其包括在计算机系统中提供设计系统，提供耦合到设计系统的布局设计工具，其中布局设计工具创建互连结构以满足电迁移标准，以及操纵设计数据库在设计系统内。

8. 发明授权

US07026225B1 Semiconductor component and method for precluding stress-induced void formation in the semiconductor component 有权
标题翻译：用于排除半导体部件中的应力诱导的空隙形成的半导体部件和方法
公开(公告)号：US07026225B1
公开(公告)日：2006-04-11
申请号：US10697214
申请日：2003-10-29
申请人： Christine Hau-Riege , Amit Marathe , John Sanchez, Jr.
发明人： Christine Hau-Riege , Amit Marathe , John Sanchez, Jr.
IPC分类号： H01L21/4163 , H01L21/326 , H01L21/479
CPC分类号： H01L21/76838 , H01L23/528 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component having a feature suitable for inhibiting stress induced void formation and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A layer of dielectric material is formed over the major surface. A metallization system is formed over the layer of dielectric material, wherein the metallization system includes a portion having gaps or apertures which inhibit stress induced void formation.
摘要翻译：具有适合于抑制应力诱导的空隙形成的特征的半导体部件和半导体部件的制造方法。提供具有主表面的半导体衬底。在主表面上形成介电材料层。在电介质材料层上形成金属化系统，其中金属化系统包括具有间隙或孔的部分，其抑制应力诱导的空隙形成。

9. 发明授权

US06822437B1 Interconnect test structure with slotted feeder lines to prevent stress-induced voids 失效
标题翻译：互连测试结构与开槽馈线，以防止应力引起的空隙
公开(公告)号：US06822437B1
公开(公告)日：2004-11-23
申请号：US10361239
申请日：2003-02-10
申请人： Christine Hau-Riege , John Sanchez , Amit P. Marathe
发明人： Christine Hau-Riege , John Sanchez , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L22/34
摘要： An interconnect test structure for characterizing electromigration includes a test line and a feeder coupled to the test line by a via structure. A width of the feeder line is greater than a width of the test line. Slots are formed in the feeder line for preventing formation of a stress-induced void at an interface between the feeder line and the via structure. Thus, an increase in resistance of the test structure is attributable to electromigration failure of the test line.
摘要翻译：用于表征电迁移的互连测试结构包括通过通孔结构连接到测试线的测试线和馈线。馈线的宽度大于测试线的宽度。在馈线中形成槽，用于防止在馈线和通孔结构之间的界面处形成应力引起的空隙。因此，测试结构的电阻增加归因于测试线的电迁移故障。

10. 发明授权

US06818557B1 Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance 有权
标题翻译：形成SiC盖铜互连的方法，具有降低的丘丘形成和改善的电迁移阻力
公开(公告)号：US06818557B1
公开(公告)日：2004-11-16
申请号：US10317053
申请日：2002-12-12
申请人： Minh Van Ngo , Christine Hau-Riege , Steve Avanzino , Robert A. Huertas
发明人： Minh Van Ngo , Christine Hau-Riege , Steve Avanzino , Robert A. Huertas
IPC分类号： H01L2144
CPC分类号： H01L21/76883 , C23C16/0245 , C23C16/325 , H01L21/3148 , H01L21/32136 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, shutting off the power, discontinuing the N2 flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.
摘要翻译：封接的Cu或Cu合金互连的电迁移阻力得到显着改善，并且通过用含有NH 3和N 2的等离子体依次和连续地处理埋入的Cu的暴露的平坦化表面，显着地降低了小丘形成，加快引入三甲基硅烷，然后引发沉积碳化硅盖层。实施方案包括用用N 2稀释的软NH 3等离子体处理嵌入的Cu的暴露表面，切断电源，停止N 2流并引入He，然后在三个阶段升高引入三甲基硅烷，然后引发等离子体增强化学同时在整个等离子体处理和碳化硅覆盖层沉积期间保持基本相同的335℃的温度。实施例还包括形成在介电常数（k）小于3.9的介电材料中形成的Cu双镶嵌结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式