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1. 发明授权

US06645052B2 Method and apparatus for controlling CMP pad surface finish 失效
公开(公告)号：US06645052B2
公开(公告)日：2003-11-11
申请号：US10039749
申请日：2001-10-26
申请人： Alan J. Jensen , Mario Stella , Eugene Zhao , Peter Renteln , Jeffrey Farber
发明人： Alan J. Jensen , Mario Stella , Eugene Zhao , Peter Renteln , Jeffrey Farber
IPC分类号： B24B100
CPC分类号： B24B37/26 , B24B21/04 , B24B37/24 , B24B49/04 , B24B53/017
摘要： A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.

2. 发明授权

US06939207B2 Method and apparatus for controlling CMP pad surface finish 失效
标题翻译：用于控制CMP垫表面光洁度的方法和设备
公开(公告)号：US06939207B2
公开(公告)日：2005-09-06
申请号：US10678727
申请日：2003-10-03
申请人： Alan J. Jensen , Mario Stella , Eugene Zhao , Peter Renteln , Jeffrey Farber
发明人： Alan J. Jensen , Mario Stella , Eugene Zhao , Peter Renteln , Jeffrey Farber
IPC分类号： B24B21/04 , B24B37/24 , B24B37/26 , B24B49/04 , B24B53/007 , B24B53/017 , B24B1/00
CPC分类号： B24B37/26 , B24B21/04 , B24B37/24 , B24B49/04 , B24B53/017
摘要： A method and apparatus for pre-conditioning a polishing pad for use in chemical mechanical planarization of semiconductor wafers is described. The apparatus includes a pre-conditioning member having a smooth surface. The method includes providing a pre-conditioning member having a smooth surface, pressing the pre-conditioning member against the polishing pad while moving the polishing pad, and flattening the surface of the polishing pad until a polishing pad flatness is achieved that may be used to achieve a desired semiconductor wafer planarity.
摘要翻译：描述了用于预处理用于半导体晶片的化学机械平面化的抛光垫的方法和装置。该装置包括具有光滑表面的预调节构件。该方法包括提供具有光滑表面的预调节构件，在移动抛光垫的同时将预处理构件压靠在抛光垫上，并且使抛光垫的表面变平，直到达到抛光垫平整度，其可以用于实现期望的半导体晶片平面度。

3. 发明授权

US06776917B2 Chemical mechanical polishing thickness control in magnetic head fabrication 失效
标题翻译：磁头制造中化学机械抛光厚度控制
公开(公告)号：US06776917B2
公开(公告)日：2004-08-17
申请号：US09754235
申请日：2001-01-03
申请人： Richard Hsiao , Son Van Nguyen , Thao Pham , Eugene Zhao
发明人： Richard Hsiao , Son Van Nguyen , Thao Pham , Eugene Zhao
IPC分类号： B44C122
CPC分类号： B24B37/013 , B24B37/048 , G11B5/3116 , G11B5/3163 , G11B5/3166 , G11B5/3173
摘要： The method for controlling the depth of polishing during a CMP process involves the deposition of a polishing stop layer at an appropriate point in the device fabrication process. The stop layer is comprised of a substance that is substantially more resistant to polishing with a particular polishing slurry that is utilized in the CMP process than a polishable material layer. Preferred stop layer materials of the present invention are tantalum and diamond-like carbon (DLC), and the polishable layer may consist of alumina. In one embodiment of the present invention the stop layer is deposited directly onto the top surface of components to be protected during the CMP process. A polishable layer is thereafter deposited upon the stop layer, and the CMP polishing step removes the polishable material layer down to the portions of the stop layer that are deposited upon the top surfaces of the components. The stop layer is thereafter removed from the top surface of the components. In this embodiment, the fabricated height of the components is preserved.
摘要翻译：用于控制CMP工艺中的抛光深度的方法包括在器件制造工艺中的适当点沉积抛光停止层。止挡层由对CMP工艺中使用的特定抛光浆料比抛光材料层基本上更耐磨的物质组成。本发明优选的停止层材料是钽和类金刚石碳（DLC），并且可抛光层可由氧化铝组成。在本发明的一个实施例中，在CMP工艺期间，停止层直接沉积在待保护部件的顶表面上。然后在停止层上沉积可抛光层，并且CMP抛光步骤将可抛光材料层除去沉积在部件顶表面上的停止层的部分。此后，从组件的顶表面去除停止层。在该实施例中，保持了部件的制造高度。

4. 发明授权

US07340360B1 Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness 有权
标题翻译：通过氧化物厚度的缩放来确定具有应力电压窗分析延伸的半导体器件的投射寿命的方法
公开(公告)号：US07340360B1
公开(公告)日：2008-03-04
申请号：US11349076
申请日：2006-02-08
申请人： John Zhang , Kurt Taylor , Eugene Zhao , Amit Marathe , Rolf Geilenkeuser , Joerg-Oliver Weidner
发明人： John Zhang , Kurt Taylor , Eugene Zhao , Amit Marathe , Rolf Geilenkeuser , Joerg-Oliver Weidner
IPC分类号： G06F19/00
CPC分类号： G01R31/2848
摘要： A method for efficiently and accurately measuring a maximum Vcc calculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vce extraction.
摘要翻译：用于有效和准确地测量微处理器和其他半导体产品的最大V cc计算或故障率和寿命投影的方法分析地将施加于较薄氧化物的低电压缩放为较厚的氧化物。从而获得更接近使用电压的扩展电压窗，从而提供精确的电压加速因子和最大提取。

5. 发明授权

US06798230B1 Structure and method for increasing accuracy in predicting hot carrier injection (HCI) degradation in semiconductor devices 失效
标题翻译：用于提高半导体器件中热载流子注入（HCI）劣化预测精度的结构和方法
公开(公告)号：US06798230B1
公开(公告)日：2004-09-28
申请号：US10346461
申请日：2003-01-15
申请人： Kurt Taylor , Jay Chan , Eugene Zhao
发明人： Kurt Taylor , Jay Chan , Eugene Zhao
IPC分类号： G01R3128
CPC分类号： H01L22/34
摘要： Aspects for increasing accuracy in predicting HCI degradation in semiconductor devices are described. The aspects include a gated ring oscillator structure utilized to perform HCI degradation testing with controlling of the gated ring oscillator structure to isolate voltage acceleration degradation from frequency degradation directly during the HCI degradation testing. Further included is a plurality of ring oscillators coupled in series, and first and second control logic for the plurality of ring oscillators for enabling selection of gated operation of the plurality of ring oscillators, wherein each ring oscillator performs a same number of transitions to allow an accurate assessment of HCI degradation based solely on voltage acceleration.
摘要翻译：描述了提高半导体器件中HCI降解精度的方面。这些方面包括门控环形振荡器结构，用于通过控制门控环形振荡器结构来执行HCI降级测试，以在HCI劣化测试期间直接将电压加速度退化与频率降低隔离。还包括串联耦合的多个环形振荡器，以及用于多个环形振荡器的第一和第二控制逻辑，用于使得能够选择多个环形振荡器的门控操作，其中每个环形振荡器执行相同数量的转换以允许仅基于电压加速度对HCI退化进行准确评估。

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