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1. 发明授权

US06630741B1 Method of reducing electromigration by ordering zinc-doping in an electroplated copper-zinc interconnect and a semiconductor device thereby formed 有权
标题翻译：通过在电镀铜 - 锌互连和由此形成的半导体器件中排序锌掺杂来减少电迁移的方法
公开(公告)号：US06630741B1
公开(公告)日：2003-10-07
申请号：US10016645
申请日：2001-12-07
申请人： Sergey Lopatin , Paul L. King , Joffre F. Bernard
发明人： Sergey Lopatin , Paul L. King , Joffre F. Bernard
IPC分类号： H01L2352
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76849 , H01L21/76858 , H01L21/76873 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing electromigration in a graded reduced-oxygen dual-inlaid copper interconnect line by filling a via with a graded Cu-rich Cu—Zn alloy fill electroplated on a Cu surface using a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a graded reduced-oxygen Cu—Zn alloy as fill for the via in forming the dual-inlaid interconnect structure. The graded alloy fill is formed by electroplating, while varying electroplating parameters, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the graded fill on the Cu surface; and annealing the electroplated graded Cu—Zn alloy fill; and planarizing the Cu—Zn alloy fill, thereby forming the graded reduced-oxygen dual-inlaid copper interconnect line.
摘要翻译：通过使用稳定的化学溶液电镀在Cu表面上的分级富Cu Cu-Zn合金填充通孔，并且通过控制和排序Zn来减少分级的还原氧双嵌入铜互连线中的电迁移的方法并且还提高了互连可靠性和耐腐蚀性，并且由此形成了半导体器件。该方法包括在形成双镶嵌互连结构中使用渐变的还原氧Cu-Zn合金作为通孔的填充物。分级合金填充是通过电镀而形成的，而不同的电镀参数，Cu表面在独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂中，从而将分级填料电镀在Cu表面上; 并对电镀分级的Cu-Zn合金填料进行退火; 并且对Cu-Zn合金填充物进行平坦化，从而形成分级的还原氧双嵌入铜互连线。

2. 发明授权

US06624074B1 Method of fabricating a semiconductor device by calcium doping a copper surface using a chemical solution 有权
标题翻译：使用化学溶液通过钙掺杂铜表面制造半导体器件的方法
公开(公告)号：US06624074B1
公开(公告)日：2003-09-23
申请号：US10218532
申请日：2002-08-13
申请人： Sergey Lopatin , Joffre F. Bernard , Paul L. King
发明人： Sergey Lopatin , Joffre F. Bernard , Paul L. King
IPC分类号： H01L2144
CPC分类号： H01L21/7685 , H01L21/288 , H01L21/76862 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X═C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.2-5% Ca) on the Cu surface of an interconnect for maximizing Ca—Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH3) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca—Cu/Cu interconnect structure.
摘要翻译：通过成本有效地沉积Cu-Ca-X表面并随后除去其中包含的污染物层，制造在Cu互连上形成的具有污染减少的Ca掺杂的Cu表面的半导体器件的方法; 和由此形成的装置。在污染物X = C，S和O的Cu-Ca-X表面中，通过（a）将Cu互连表面浸入包含Cu盐，Ca盐，它们的络合剂，还原剂，pH调节剂和用于促进Cu互连材料的Ca掺杂的至少一种表面活性剂; （b）将Cu-Ca-X表面在真空下退火到下面的Cu互连材料上，以在Cu互连结构上形成Cu-Ca膜，从而产生均匀的Cu-Ca膜（即富含Cu- 5％Ca）在铜互连的Cu表面，以最大限度地提高Ca-Cu / Cu互连结构的可靠性，抗电迁移和防腐蚀。退火步骤主要去除O，并且二次除去C和S，特别是在真空，惰性气体或还原环境如氨（NH 3）等离子体下进行时）。因此，所得到的器件然后包括不同的污染物减少的Ca-Cu / Cu互连结构。

3. 发明授权

US06621165B1 Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface 有权
标题翻译：通过在掺杂钙的铜表面中还原碳，硫和氧杂质制造的半导体器件
公开(公告)号：US06621165B1
公开(公告)日：2003-09-16
申请号：US10154871
申请日：2002-05-23
申请人： Sergey Lopatin , Paul L. King , Joffre F. Bernard
发明人： Sergey Lopatin , Paul L. King , Joffre F. Bernard
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/288 , H01L21/76838 , H01L21/76862 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects fabricated by cost-effectively removing the contaminant layer. Contaminant removal from a Cu—Ca—X surface, where contaminant X═C, S, or O, is achieved by sputtering the Cu—Ca—X surface in an argon (Ar) atmosphere between the steps of (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Ca—Cu alloy surface onto the underlying Cu interconnect material to form a Ca—Cu/Cu interconnect structure, whereby the sputtering step, under Ar, selectively and effectively removes contaminants from the Cu—Ca—X layer containing higher concentrations of C, S, or O, thereby minimizing the post-annealed contaminant level, and thereby producing a uniform Ca—Cu alloy surface (i.e., Cu-rich with 0.2-5% Ca) on the Cu interconnect material for maximizing Ca—Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH3) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Ca—Cu/Cu interconnect structure.
摘要翻译：具有通过成本有效地去除污染物层而制造的Cu互连上形成污染物降低的钙 - 铜（Ca-Cu）合金表面的半导体器件。污染物X = C，S或O的Cu-Ca-X表面的污染物去除是通过在氩（Ar）气氛中溅射Cu-Ca-X表面，在（a）浸渍Cu 将互连表面连接成包含Cu盐，Ca盐，它们的络合剂，还原剂，pH调节剂和至少一种用于促进Cu互连材料的Ca掺杂的表面活性剂的化学镀溶液; 和（b）将Ca-Cu合金表面退火到下面的Cu互连材料上以形成Ca-Cu / Cu互连结构，由此在Ar下的溅射步骤选择性且有效地从Cu-Ca-X层去除污染物含有较高浓度的C，S或O，从而使退火后的污染物水平最小化，从而在Cu互连材料上产生均匀的Ca-Cu合金表面（即，具有0.2-5％Ca的富含Cu的Cu），以使 Ca-Cu / Cu互连结构的可靠性，电迁移性和防腐蚀性。退火步骤主要去除O，并且二次除去C和S，特别是在真空，惰性气体或还原环境如氨（NH 3）等离子体下进行时）。因此，所得到的器件然后包括不同的污染物减少的Ca-Cu / Cu互连结构。

4. 发明授权

US06611576B1 Automated control of metal thickness during film deposition 失效
标题翻译：膜沉积期间金属厚度的自动控制
公开(公告)号：US06611576B1
公开(公告)日：2003-08-26
申请号：US09780476
申请日：2001-02-12
申请人： Paul R. Besser , Paul L. King
发明人： Paul R. Besser , Paul L. King
IPC分类号： G01N23223
CPC分类号： C23C14/545 , G01N23/223 , G01N2223/076
摘要： A novel method of automatically controlling thickness of a metal film during film deposition in a deposition chamber. The method involves producing an X-ray beam directed to the metal film deposited on a wafer in a deposition chamber, and detecting X-ray fluorescence of the metal film. The thickness of the metal film determined based on the detected X-ray fluorescence is compared with a preset value to continue deposition if the determined thickness is less than the preset value. Deposition is stopped when the determined thickness reaches the preset value.
摘要翻译：一种在淀积室中成膜期间自动控制金属膜厚度的新方法。该方法包括产生指向沉积在沉积室中的晶片上的金属膜的X射线束，并且检测金属膜的X射线荧光。如果确定的厚度小于预设值，则将基于检测到的X射线荧光确定的金属膜的厚度与预设值进行比较以继续沉积。当确定的厚度达到预设值时，停止沉积。

5. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

6. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

7. 发明授权

US06297107B1 High dielectric constant materials as gate dielectrics 有权
标题翻译：高介电常数材料作为栅极电介质
公开(公告)号：US06297107B1
公开(公告)日：2001-10-02
申请号：US09691228
申请日：2000-10-19
申请人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
发明人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.
摘要翻译：通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

8. 发明授权

US4181194A Safety clamp device and apparatus utilizing same 失效
标题翻译：安全钳装置及利用该装置的装置
公开(公告)号：US4181194A
公开(公告)日：1980-01-01
申请号：US914277
申请日：1978-06-09
申请人： James H. Bassett , Paul L. King
发明人： James H. Bassett , Paul L. King
IPC分类号： E04G3/32 , E04G3/10
CPC分类号： E04G3/32 , Y10T24/3949
摘要： An improved safety clamp device for use with movable platforms and the like includes a body member having a safety cable receiving cradle, a lever arm having a safety cable engaging portion, the lever arm being pivotally connected to the body member and pivotally connected to an elongate bar member, and a modified bellcrank. The modified bellcrank has a first arm pivotally connected to the body member, a second arm pivotally coupled to a hoist line, and its apex pivotally connected to the elongate bar member. When the elongate bar member is in a first position relative to the body member, the safety cable engaging portion confronts but does not engage the safety cable. When the elongate bar member is in a second position relative to the body member, the safety cable engaging portion engages the safety cable thereby wedging the safety cable between the cradle and the safety cable engaging portions. The modified bellcrank and the lever arm operate cooperatively to maintain the body member and the elongate bar member in parallel relationship to the safety cable.
摘要翻译：一种用于可移动平台等的改进的安全夹紧装置包括具有安全电缆接收支架的主体构件，具有安全缆线接合部分的杠杆臂，杠杆臂可枢转地连接到主体构件并枢转地连接到细长酒吧会员和修改后的曲拐。改进的曲拐具有枢转地连接到主体构件的第一臂，枢转地联接到提升线的第二臂，并且其顶点枢转地连接到细长杆构件。当细长杆构件相对于主体构件处于第一位置时，安全缆线接合部分面对但不接合安全缆线。当细长杆构件相对于主体构件处于第二位置时，安全缆线接合部分接合安全缆线，从而将安全缆线楔入托架和安全缆线接合部分之间。改进的曲拐和杠杆臂协同工作以使主体构件和细长杆构件保持与安全缆线平行的关系。

9. 发明授权

US07250667B2 Selectable open circuit and anti-fuse element 有权
标题翻译：可选开路和反熔丝元件
公开(公告)号：US07250667B2
公开(公告)日：2007-07-31
申请号：US11306663
申请日：2006-01-05
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。源极/漏极结在半导体衬底中。硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。层间电介质在半导体衬底之上。触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

10. 发明授权

US07151020B1 Conversion of transition metal to silicide through back end processing in integrated circuit technology 有权
标题翻译：在集成电路技术中通过后端处理将过渡金属转化为硅化物
公开(公告)号：US07151020B1
公开(公告)日：2006-12-19
申请号：US10839437
申请日：2004-05-04
申请人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
发明人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成过渡金属层。在半导体衬底上形成层间电介质。然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。

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