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1. 发明授权

US08543722B2 Message passing with queues and channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US08543722B2
公开(公告)日：2013-09-24
申请号：US12750363
申请日：2010-03-30
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow , Robert W. Wisniewski
IPC分类号： G06F15/16
CPC分类号： G06F9/546
摘要： In an embodiment, a send thread receives an identifier that identifies a destination node and a pointer to data. The send thread creates a first send request in response to the receipt of the identifier and the data pointer. The send thread selects a selected channel from among a plurality of channels. The selected channel comprises a selected hand-off queue and an identification of a selected message unit. Each of the channels identifies a different message unit. The selected hand-off queue is randomly accessible. If the selected hand-off queue contains an available entry, the send thread adds the first send request to the selected hand-off queue. If the selected hand-off queue does not contain an available entry, the send thread removes a second send request from the selected hand-off queue and sends the second send request to the selected message unit.
摘要翻译：在一个实施例中，发送线程接收标识目的地节点的标识符和指向数据的指针。响应于接收到标识符和数据指针，发送线程创建第一个发送请求。发送线程从多个信道中选择所选择的信道。所选择的信道包括所选择的切换队列和所选择的消息单元的标识。每个通道标识不同的消息单元。所选择的切换队列是随机访问的。如果所选择的切换队列包含可用条目，则发送线程将第一个发送请求添加到所选择的切换队列。如果所选择的切换队列不包含可用条目，则发送线程从所选择的切换队列中移除第二发送请求，并将第二发送请求发送到所选择的消息单元。

2. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

3. 发明申请

US20110179229A1 STORE-OPERATE-COHERENCE-ON-VALUE 有权
标题翻译：存储操作相关值
公开(公告)号：US20110179229A1
公开(公告)日：2011-07-21
申请号：US12986652
申请日：2011-01-07
申请人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/3834 , Y02D10/13
摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
摘要翻译：一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。系统中的硬件单元运行接收到的存储操作指令。硬件单元评估运行接收到的存储操作指令的结果是否满足条件。如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

4. 发明申请

US20090007141A1 MESSAGE PASSING WITH A LIMITED NUMBER OF DMA BYTE COUNTERS 失效
标题翻译：消息传递与有限数量的DMA字节计数器
公开(公告)号：US20090007141A1
公开(公告)日：2009-01-01
申请号：US11768813
申请日：2007-06-26
申请人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F9/44
CPC分类号： G06F15/17356 , G06F9/546
摘要： A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to send (CTS) message to the source node in a rendezvous protocol form of a remote get to accept the RTS message and message data and processing the remote get (CTS) by the source compute node DMA engine to provide the message data to be sent.
摘要翻译：一种在并行计算机系统中传送消息的方法，该并行计算机系统被构造为作为网络互连的多个计算节点，其中每个计算节点包括DMA引擎，但是仅包括有限数量的字节计数器，用于跟踪由 DMA引擎，其中可以在共享计数器或专用计数器操作模式中使用字节计数器。该方法包括使用会合协议，源计算节点使用专用注入计数器确定性地发送具有单个RTS描述符的请求（RTS）消息以跟踪要与RTS消息相关联地发送的RTS消息和消息数据，到目的地计算节点，使得RTS描述符向目标计算节点指示消息数据将自适应地路由到目的地节点。在源计算节点使用一个DMA FIFO，将为发往目的地计算节点的会合消息保留RTS描述符，以确保正确的消息数据顺序。在DMA引擎上使用接收计数器，目的地计算节点跟踪RTS和相关联的消息数据的接收，并以远程获取的会合协议形式向源节点发送明确发送（CTS）消息以接受RTS消息和消息数据，并由源计算节点DMA引擎处理远程获取（CTS）以提供要发送的消息数据。

5. 发明申请

US20110265098A1 Message Passing with Queues and Channels 失效
标题翻译：消息传递与队列和通道
公开(公告)号：US20110265098A1
公开(公告)日：2011-10-27
申请号：US12764315
申请日：2010-04-21
申请人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow
发明人： Gabor J. Dozsa , Philip Heidelberger , Sameer Kumar , Joseph D. Ratterman , Burkhard Steinmacher-Burow
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F2209/548
摘要： In an embodiment, a reception thread receives a source node identifier, a type, and a data pointer from an application and, in response, creates a receive request. If the source node identifier specifies a source node, the reception thread adds the receive request to a fast-post queue. If a message received from a network does not match a receive request on a posted queue, a polling thread adds a receive request that represents the message to an unexpected queue. If the fast-post queue contains the receive request, the polling thread removes the receive request from the fast-post queue. If the receive request that was removed from the fast-post queue does not match the receive request on the unexpected queue, the polling thread adds the receive request that was removed from the fast-post queue to the posted queue. The reception thread and the polling thread execute asynchronously from each other.
摘要翻译：在一个实施例中，接收线程从应用接收源节点标识符，类型和数据指针，作为响应，创建接收请求。如果源节点标识符指定源节点，则接收线程将接收请求添加到快速发送队列。如果从网络接收到的消息与发布的队列上的接收请求不匹配，轮询线程将将消息的接收请求添加到意外队列。如果快速发送队列包含接收请求，轮询线程将从快速发送队列中删除接收请求。如果从快速发布队列中删除的接收请求与意外队列中的接收请求不匹配，轮询线程将从快速发布队列中删除的接收请求添加到发布的队列。接收线程和轮询线程彼此异步执行。

6. 发明授权

US08032892B2 Message passing with a limited number of DMA byte counters 失效
标题翻译：消息传递有限数量的DMA字节计数器
公开(公告)号：US08032892B2
公开(公告)日：2011-10-04
申请号：US11768813
申请日：2007-06-26
申请人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
发明人： Michael Blocksome , Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker
IPC分类号： G06F9/44 , G06F9/46 , G06F13/00 , G06F15/167
CPC分类号： G06F15/17356 , G06F9/546
摘要： A method for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA engine, where the byte counters may be used in shared counter or exclusive counter modes of operation. The method includes using rendezvous protocol, a source compute node deterministically sending a request to send (RTS) message with a single RTS descriptor using an exclusive injection counter to track both the RTS message and message data to be sent in association with the RTS message, to a destination compute node such that the RTS descriptor indicates to the destination compute node that the message data will be adaptively routed to the destination node. Using one DMA FIFO at the source compute node, the RTS descriptors are maintained for rendezvous messages destined for the destination compute node to ensure proper message data ordering thereat. Using a reception counter at a DMA engine, the destination compute node tracks reception of the RTS and associated message data and sends a clear to send (CTS) message to the source node in a rendezvous protocol form of a remote get to accept the RTS message and message data and processing the remote get (CTS) by the source compute node DMA engine to provide the message data to be sent.
摘要翻译：一种在并行计算机系统中传送消息的方法，该并行计算机系统被构造为作为网络互连的多个计算节点，其中每个计算节点包括DMA引擎，但是仅包括有限数量的字节计数器，用于跟踪由 DMA引擎，其中可以在共享计数器或专用计数器操作模式中使用字节计数器。该方法包括使用会合协议，源计算节点使用专用注入计数器确定性地发送具有单个RTS描述符的请求（RTS）消息以跟踪要与RTS消息相关联地发送的RTS消息和消息数据，到目的地计算节点，使得RTS描述符向目标计算节点指示消息数据将自适应地路由到目的地节点。在源计算节点使用一个DMA FIFO，将为发往目的地计算节点的会合消息保留RTS描述符，以确保正确的消息数据顺序。在DMA引擎上使用接收计数器，目的地计算节点跟踪RTS和相关联的消息数据的接收，并以远程获取的会合协议形式向源节点发送明确发送（CTS）消息以接受RTS消息和消息数据，并由源计算节点DMA引擎处理远程获取（CTS）以提供要发送的消息数据。

7. 发明申请

US20110072241A1 FAST CONCURRENT ARRAY-BASED STACKS, QUEUES AND DEQUES USING FETCH-AND-INCREMENT-BOUNDED AND A TICKET LOCK PER ELEMENT 有权
标题翻译：基于阵列的快速堆叠堆栈，使用边界加密和每个元素的门票锁定的排队和排序
公开(公告)号：US20110072241A1
公开(公告)日：2011-03-24
申请号：US12564535
申请日：2009-09-22
申请人： Dong Chen , Alana Gara , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert Wisniewski
发明人： Dong Chen , Alana Gara , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert Wisniewski
IPC分类号： G06F9/38 , G06F15/76
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/526 , G06F9/546
摘要： Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues.
摘要翻译：提供了基于并发数组的堆栈，队列，双端队列（deques）和包装deques的实现原语。在一个方面，堆栈，队列，deque或包装的deque数据结构的每个元素都有自己的票证锁定，允许多个线程同时使用数据结构的多个元素，从而实现高性能。在另一方面，实现新的同步原语FetchAndIncrementBounded（Counter，Bound）和FetchAndDecrementBounded（Counter，Bound）。这些原语可以在硬件中实现，从而为队列，堆栈和双端队列提供非常快的吞吐量。

8. 发明申请

US20110010471A1 Recording A Communication Pattern and Replaying Messages in a Parallel Computing System 失效
标题翻译：在并行计算系统中记录通信模式和回放消息
公开(公告)号：US20110010471A1
公开(公告)日：2011-01-13
申请号：US12500715
申请日：2009-07-10
申请人： Philip Heidelberger , Sameer Kumar
发明人： Philip Heidelberger , Sameer Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.
摘要翻译：并行计算机系统包括多个计算节点。每个计算节点包括耦合到至少一个处理器和至少一个存储器的至少一个处理器，至少一个存储器和直接存储器地址引擎。该系统还包括互连多个计算节点的网络。该网络运行全球消息传递应用程序，用于跨网络执行通信。全局消息传递应用的本地实例在每个计算节点处操作，以独立于在另一个计算节点处执行的处理操作来执行本地处理操作。直接存储器地址引擎被配置为通过描述在对应的一个存储器中的注入FIFO的注入FIFO元数据与全局消息传递应用的本地实例进行交互。全局消息传递应用程序的本地实例被配置为在执行的应用程序的迭代中在对应的一个存储器中的注入FIFO中记录与任意通信模式的消息相关联的消息描述符。全局消息传递应用程序的本地实例被配置为在执行的应用程序的后续迭代期间重播消息描述符。

9. 发明申请

US20080307121A1 Direct Memory Access Transfer Completion Notification 失效
标题翻译：直接内存访问传输完成通知
公开(公告)号：US20080307121A1
公开(公告)日：2008-12-11
申请号：US11758167
申请日：2007-06-05
申请人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Mark E. Giampapa , Philip Heidelberger , Sameer Kumar , Jeffrey J. Parker , Burkhard D. Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.
摘要翻译：提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

10. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

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