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1. 发明申请

US20060017066A1 Methods of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US20060017066A1
公开(公告)日：2006-01-26
申请号：US11231385
申请日：2005-09-21
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

2. 发明申请

US20050199908A1 METHOD OF BASE FORMATION IN A BICMOS PROCESS 失效
标题翻译： BICMOS过程中基质形成的方法
公开(公告)号：US20050199908A1
公开(公告)日：2005-09-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

3. 发明申请

US20070077760A1 METHOD AND APPARATUS FOR FORMING NICKEL SILICIDE WITH LOW DEFECT DENSITY IN FET DEVICES 有权
标题翻译：在FET器件中形成具有低缺陷密度的镍硅氧烷的方法和装置
公开(公告)号：US20070077760A1
公开(公告)日：2007-04-05
申请号：US11163038
申请日：2005-10-03
申请人： Keith Wong , Robert Purtell
发明人： Keith Wong , Robert Purtell
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , C23C14/16 , C23C14/32 , C23C14/345 , H01L21/28052 , H01L21/2855 , H01L29/66507 , H01L29/78
摘要： A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.
摘要翻译：提供了一种方法和装置，其中在相同的处理室中执行非定向和定向金属（例如Ni）沉积步骤。形成第一等离子体以从靶中去除材料; 在连接到RF发生器的环形电极（例如Ni环）的内部形成用于增加材料中的离子密度的二次等离子体。在不存在基板的二次等离子体和电偏置的情况下，材料被非定向地沉积在基板上，并且当存在二次等离子体并且基板被电偏置时定向沉积材料。由沉积金属形成的硅化镍具有较低的栅极多晶硅薄层电阻，并且可能具有比仅在单向定向工艺中沉积的金属形成的NiSi更低的管缺陷密度，并且具有比由金属沉积形成的NiSi更低的源/漏接触电阻在一个单一的无方向的过程。

4. 发明申请

US20060057844A1 STRUCTURE AND METHOD FOR ENHANCED UNI-DIRECTIONAL DIFFUSION OF COBALT SILICIDE 失效
标题翻译：碳酸硅酮增强单向扩散的结构与方法
公开(公告)号：US20060057844A1
公开(公告)日：2006-03-16
申请号：US10711365
申请日：2004-09-14
申请人： Anthony Domenicucci , Bradley Jones , Christian Lavoie , Robert Purtell , Yun Yu Wang , Kwong Hon Wong
发明人： Anthony Domenicucci , Bradley Jones , Christian Lavoie , Robert Purtell , Yun Yu Wang , Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665
摘要： The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.
摘要翻译：本发明提供了一种通过使用含金属的硅合金与进行两个不同的热循环的第一次退火相结合的方法来增强金属在硅化过程中的单向扩散。第一退火的第一热循环在能够增强金属例如Co和/或Ni的单向扩散到含Si层中的温度下进行。第一热循环导致形成含非晶态金属的硅化物。第二热循环在将含非晶态金属的硅化物转化为与含金属的硅合金层或纯金属含有层相比基本上不可蚀刻的结晶的富含金属的硅化物的温度下进行。在第一退火之后，执行选择性蚀刻以从结构中除去任何未反应的含金属合金层。执行第二退火以将由第一退火的两个热循环形成的富金属硅化物相转换成处于其最低电阻相的金属硅化物相。提供了一种金属硅化物，其厚度是自限制的。

5. 发明申请

US20050067745A1 Method and apparatus for deposition & formation of metal silicides 审中-公开
标题翻译：用于沉积和形成金属硅化物的方法和装置
公开(公告)号：US20050067745A1
公开(公告)日：2005-03-31
申请号：US10674302
申请日：2003-09-30
申请人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
发明人： Kenneth Giewont , Bradley Jones , Christian Lavoie , Robert Purtell , Yun-Yu Wang , Kwong Wong
IPC分类号： C22F1/00 , C23C14/16 , C23C14/58
CPC分类号： C23C14/5806 , C23C14/16
摘要： Disclosed is a method and structure for forming a silicide on a silicon material. The invention places the silicon material in a vacuum environment, forms metal on the silicon material, and then heats the silicon surface and the metal without breaking the vacuum environment. The processes of forming the metal and heating the silicon can be performed simultaneously without breaking the vacuum environment to form the silicide as the metal is being deposited. After the foregoing processing, the invention can remove the silicon surface from the vacuum environment and perform additional heating of the silicon surface. The first heating process forms a monosilicide and the additional heating forms a disilicide.
摘要翻译：公开了一种在硅材料上形成硅化物的方法和结构。本发明将硅材料置于真空环境中，在硅材料上形成金属，然后在不破坏真空环境的情况下加热硅表面和金属。当金属沉积时，形成金属和加热硅的工艺可以同时进行而不破坏真空环境以形成硅化物。在上述处理之后，本发明可以从真空环境中去除硅表面，并对硅表面进行附加加热。第一加热工艺形成一硅化物，另外的加热形成二硅化物。

6. 发明申请

US20070161240A1 AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS 有权
标题翻译：用于改进硅酸盐形成与复合CAPS的空气破裂
公开(公告)号：US20070161240A1
公开(公告)日：2007-07-12
申请号：US11306719
申请日：2006-01-09
申请人： Robert Purtell , Keith Wong
发明人： Robert Purtell , Keith Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.
摘要翻译：公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。然而，在沉积第二金属层之前，保护层暴露于空气中。这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。结果是对于n-FET性能最佳的更强的硅化物。此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在栅极导体和侧壁间隔件，以避免硅桥接。

7. 发明申请

US20060163671A1 SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
标题翻译：减少应力和改进的栅格电阻的硅胶结构和工艺
公开(公告)号：US20060163671A1
公开(公告)日：2006-07-27
申请号：US10905949
申请日：2005-01-27
申请人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/665
摘要： A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.
摘要翻译：一种自杀帽结构和制造具有低薄层阻力的自杀帽的方法。该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

8. 发明申请

US20080020535A1 SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
标题翻译：减少应力和改进的栅格电阻的硅胶结构和工艺
公开(公告)号：US20080020535A1
公开(公告)日：2008-01-24
申请号：US11866751
申请日：2007-10-03
申请人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/665
摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.
摘要翻译：一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

9. 发明申请

US20070020929A1 METHOD FOR REDUCING DENDRITE FORMATION IN NICKEL SILICON SALICIDE PROCESSES 失效
标题翻译：在镍硅酸盐工艺中减少形成碳酸盐的方法
公开(公告)号：US20070020929A1
公开(公告)日：2007-01-25
申请号：US11460671
申请日：2006-07-28
申请人： Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
摘要翻译：用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构形成在其上。金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。

10. 发明申请

US20060211244A1 CLUSTERED SURFACE PREPARATION FOR SILICIDE AND METAL CONTACTS 有权
标题翻译：用于硅胶和金属接触的聚合表面处理
公开(公告)号：US20060211244A1
公开(公告)日：2006-09-21
申请号：US10907061
申请日：2005-03-18
申请人： Sadanand Deshpande , Ying Li , Kevin Mello , Renee Mo , Wesley Natzle , Kirk Peterson , Robert Purtell
发明人： Sadanand Deshpande , Ying Li , Kevin Mello , Renee Mo , Wesley Natzle , Kirk Peterson , Robert Purtell
IPC分类号： H01L21/44 , C23C16/00
CPC分类号： H01L21/28518 , C23C16/0227 , H01L21/02057 , H01L21/28512 , H01L21/67207 , H01L21/67745
摘要： A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.
摘要翻译：提供了一种集群工具，用于实现半导体器件表面的集群和集成表面预清洁。更具体地，提供了一种集成工具及其在集成半导体器件表面预清洁中的应用方法，其针对制造方面，其中用于在半导体上执行干法处理化学氧化物去除（COR）的室器件表面与诸如用于硅化物或接触形成的金属沉积工具的其它工具聚集，包括在簇工具中提供真空转移模块。

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