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1. 发明申请

US20100203689A1 finFET TRANSISTOR AND CIRCUIT 有权
标题翻译： finFET晶体管和电路
公开(公告)号：US20100203689A1
公开(公告)日：2010-08-12
申请号：US12762427
申请日：2010-04-19
申请人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
发明人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
摘要翻译：驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有最少一个双门翅和一个分闸门。

2. 发明申请

US20090106726A1 DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 有权
标题翻译：设计结构包括用于半导体器件中的横向电流承载能力改进的手段
公开(公告)号：US20090106726A1
公开(公告)日：2009-04-23
申请号：US11873711
申请日：2007-10-17
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：包括半导体结构的设计结构。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

3. 发明申请

US20080122096A1 METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件中的横向电流承载能力改进的方法
公开(公告)号：US20080122096A1
公开(公告)日：2008-05-29
申请号：US11460314
申请日：2006-07-27
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/8249 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：半导体结构及其形成方法。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

4. 发明授权

US06909147B2 Multi-height FinFETS 有权
标题翻译：多高度FinFETS
公开(公告)号：US06909147B2
公开(公告)日：2005-06-21
申请号：US10249738
申请日：2003-05-05
申请人： Ingo Aller , Joachim Keinert , Thomas Ludwig , Edward J. Nowak , BethAnn Rainey
发明人： Ingo Aller , Joachim Keinert , Thomas Ludwig , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/786 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/66795
摘要： The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.
摘要翻译：本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。每个散热片具有从沟道区延伸的沟道区和源极和漏极区。翅片具有不同的高度。本发明具有邻近散热片定位的栅极导体。栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。翅片彼此平行。第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

5. 发明授权

US06794718B2 High mobility crystalline planes in double-gate CMOS technology 有权
标题翻译：双栅极CMOS技术中的高迁移率晶面
公开(公告)号：US06794718B2
公开(公告)日：2004-09-21
申请号：US10248123
申请日：2002-12-19
申请人： Edward J. Nowak , BethAnn Rainey
发明人： Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L2712
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orientation orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.
摘要翻译：具有形成在基板上的第一和第二独立半导体本体的MOS器件。第一独立半导体本体具有相对于第二独立半导体本体的第一部分以非正交的非平行取向设置的第一部分。所述第一和第二独立半导体本体的这些部分具有相应的第一和第二晶体取向。第一栅电极与第二独立半导体本体的第一部分上的第二栅电极非正交角度交叉在所述第一独立半导体本体的所述第一部分的至少一部分上。

6. 发明授权

US07700446B2 Virtual body-contacted trigate 失效
标题翻译：虚拟身体接触的三位一体
公开(公告)号：US07700446B2
公开(公告)日：2010-04-20
申请号：US11830868
申请日：2007-07-31
申请人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak , BethAnn Rainey
发明人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78615 , H01L29/78687
摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.
摘要翻译：场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。优选地，SiGe层包含碳。优选地，该对第一栅极结构基本上横向于第二栅极结构。此外，该对第一栅极结构优选地被绝缘层封装。

7. 发明授权

US07470578B2 Method of making a finFET having suppressed parasitic device characteristics 有权
标题翻译：制造具有抑制寄生器件特性的finFET的方法
公开(公告)号：US07470578B2
公开(公告)日：2008-12-30
申请号：US11267882
申请日：2005-11-04
申请人： Edward J. Nowak , BethAnn Rainey
发明人： Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/785 , H01L27/1203 , H01L29/66795
摘要： A finFET (100) having sidwall spacers (136, 140) to suppress parasitic devices in the upper region of a channel and at the bases of source(s) and drain(s) that are artifacts of the fabrication techniques used to make the finFET. The FinFET is formed on an SOI wafer (104) by etching through a hardmask (148) so as to form a freestanding fin (120). Prior to doping the source(s) (124) and drain(s) (128), a layer (156) of thermal oxide is deposited over the entire finFET. This layer is etched away so as to form the sidewall spacers at each reentrant corner formed where a horizontal surface meets a vertical surface. Sidewall spacers (136) inhibit doping of the upper region of source(s) and drain(s) immediately adjacent the gate. Sidewall spacers (140) fill in any undercut regions (144) of BOX layer (116) that may have been formed during prior fabrication steps.
摘要翻译：具有侧壁间隔物（136,140）的finFET（100），其用于抑制通道上部区域中的寄生器件，以及源极和漏极的基础，这些器件是用于制造鳍状FET的制造技术的假象。 FinFET通过蚀刻穿过硬掩模（148）形成在SOI晶片（104）上，以形成独立散热片（120）。在掺杂源极（124）和漏极（128）之前，在整个finFET上沉积热氧化物层（156）。该层被蚀刻掉，以便在形成的水平表面与垂直表面相交的每个折入角处形成侧壁间隔物。侧壁间隔物（136）抑制源极的上部区域和与栅极紧邻的漏极的掺杂。侧壁间隔物（140）填充可能在先前制造步骤期间形成的BOX层（116）的任何底切区域（144）。

8. 发明申请

US20080268604A1 METHODS OF BASE FORMATION IN A BiCMOS PROCESS 失效
标题翻译： BiCMOS工艺中基质形成的方法
公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

9. 发明授权

US07368355B2 FinFET transistor and circuit 有权
标题翻译： FinFET晶体管和电路
公开(公告)号：US07368355B2
公开(公告)日：2008-05-06
申请号：US11458250
申请日：2006-07-18
申请人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
发明人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
摘要翻译：驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有最少一个双门翅和一个分闸门。

10. 发明申请

US20070023756A1 VIRTUAL BODY-CONTACTED TRIGATE 有权
标题翻译：虚拟身体接触的TRIGATE
公开(公告)号：US20070023756A1
公开(公告)日：2007-02-01
申请号：US11161213
申请日：2005-07-27
申请人： Brent Anderson , Matthew Breitwisch , Edward Nowak , BethAnn Rainey
发明人： Brent Anderson , Matthew Breitwisch , Edward Nowak , BethAnn Rainey
IPC分类号： H01L29/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78615 , H01L29/78687
摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.
摘要翻译：场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。优选地，SiGe层包含碳。优选地，该对第一栅极结构基本上横向于第二栅极结构。此外，该对第一栅极结构优选地被绝缘层封装。

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