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1. 发明申请

US20060017066A1 Methods of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US20060017066A1
公开(公告)日：2006-01-26
申请号：US11231385
申请日：2005-09-21
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

2. 发明申请

US20050199908A1 METHOD OF BASE FORMATION IN A BICMOS PROCESS 失效
标题翻译： BICMOS过程中基质形成的方法
公开(公告)号：US20050199908A1
公开(公告)日：2005-09-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

3. 发明授权

US07390721B2 Methods of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US07390721B2
公开(公告)日：2008-06-24
申请号：US11231385
申请日：2005-09-21
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

4. 发明申请

US20080268604A1 METHODS OF BASE FORMATION IN A BiCMOS PROCESS 失效
标题翻译： BiCMOS工艺中基质形成的方法
公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

5. 发明授权

US06965133B2 Method of base formation in a BiCMOS process 失效
标题翻译： BiCMOS工艺中碱形成的方法
公开(公告)号：US06965133B2
公开(公告)日：2005-11-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

6. 发明授权

US07709930B2 Tuneable semiconductor device with discontinuous portions in the sub-collector 失效
标题翻译：在子集电极中具有不连续部分的可调谐半导体器件
公开(公告)号：US07709930B2
公开(公告)日：2010-05-04
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

7. 发明申请

US20050079726A1 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
公开(公告)号：US20050079726A1
公开(公告)日：2005-04-14
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn Schonenberg , Gregory Freeman , Andreas Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn Schonenberg , Gregory Freeman , Andreas Stricker , Jae-Sung Rieh
IPC分类号： H01L21/321 , H01L21/331 , H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

8. 发明申请

US20070215978A1 TUNEABLE SEMICONDUCTOR DEVICE 失效
标题翻译：可调谐半导体器件
公开(公告)号：US20070215978A1
公开(公告)日：2007-09-20
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

9. 发明授权

US07696034B2 Methods of base formation in a BiCOMS process 失效
标题翻译： BiCOMS工艺中碱形成的方法
公开(公告)号：US07696034B2
公开(公告)日：2010-04-13
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , Beth Ann Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

10. 发明申请

US20100244113A1 MOS VARACTOR AND FABRICATING METHOD OF THE SAME 有权
标题翻译： MOS变压器及其制作方法
公开(公告)号：US20100244113A1
公开(公告)日：2010-09-30
申请号：US12565197
申请日：2009-09-23
申请人： Jae-Sung Rieh , Yong Ho Oh , Sue Yeon Kim , Seung Yong Lee
发明人： Jae-Sung Rieh , Yong Ho Oh , Sue Yeon Kim , Seung Yong Lee
IPC分类号： H01L29/93 , H01L21/329
CPC分类号： H01L29/93 , H01L29/66174
摘要： The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor. The MOS varactor include: island-like gate insulating layers which are arranged at equal intervals in the form of a (n×m) matrix (where, n and m are integers equal to or larger than one), and a gate electrode of a first height (t1) placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire of a second height (t2) (where, t1
摘要翻译：本发明提供一种用于毫米波频带的电路和元件的MOS可变电抗器，其能够通过使用位于一个或多个的区域中的多个岛状门来降低串联电阻并提高Q因子衬底和栅极直接连接在栅极上，以及制造MOS变容二极管的方法。 MOS变容二极管包括：以（n×m）矩阵（其中，n和m为1以上的整数）等间隔配置的岛状栅极绝缘层，以及栅电极第一高度（t1）放置在衬底的阱区域中的栅极绝缘层上; 接触栅电极的栅极接触; 电连接到栅极触点的第二高度（t2）（其中，t1

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