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1. 发明申请

US20080020535A1 SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
标题翻译：减少应力和改进的栅格电阻的硅胶结构和工艺
公开(公告)号：US20080020535A1
公开(公告)日：2008-01-24
申请号：US11866751
申请日：2007-10-03
申请人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/665
摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.
摘要翻译：一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

2. 发明申请

US20060163671A1 SILICIDE CAP STRUCTURE AND PROCESS FOR REDUCED STRESS AND IMPROVED GATE SHEET RESISTANCE 审中-公开
标题翻译：减少应力和改进的栅格电阻的硅胶结构和工艺
公开(公告)号：US20060163671A1
公开(公告)日：2006-07-27
申请号：US10905949
申请日：2005-01-27
申请人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
发明人： Levent Gulari , Kevin Mello , Robert Purtell , Yun-Yu Wang , Keith Wong
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/665
摘要： A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.
摘要翻译：一种自杀帽结构和制造具有低薄层阻力的自杀帽的方法。该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

3. 发明授权

US07935613B2 Three-dimensional silicon on oxide device isolation 有权
标题翻译：三维硅上氧化物的隔离
公开(公告)号：US07935613B2
公开(公告)日：2011-05-03
申请号：US10596569
申请日：2003-12-16
申请人： Levent Gulari
发明人： Levent Gulari
IPC分类号： H01L21/30
CPC分类号： B81C1/00507 , H01L21/76243 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).
摘要翻译：绝缘体上硅晶片（10）。 SOI晶片（10）包括顶部硅层（6），硅衬底（4）和跨过晶片（10）并且位于硅衬底（4）和顶部硅层之间的氧化物绝缘体层（2）（6）。氧化物绝缘体层（2）具有轮廓顶面（8a，8b，8c，8d，8e）和轮廓底面（12e）中的至少一个。还提供了用于制造这种SOI晶片（10）的工艺。

4. 发明授权

US08405150B2 Contoured insulator layer of silicon-on-insulator wafers and process of manufacture 失效
标题翻译：硅绝缘体硅片的轮廓绝缘体层及其制造工艺
公开(公告)号：US08405150B2
公开(公告)日：2013-03-26
申请号：US12987232
申请日：2011-01-10
申请人： Levent Gulari
发明人： Levent Gulari
IPC分类号： H01L29/78
CPC分类号： B81C1/00507 , H01L21/76243 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A silicon-on-insulator wafer. The SOI wafer comprises a top silicon layer, a silicon substrate, and an oxide insulator layer disposed across the wafer and between the silicon substrate and the top silicon layer. The oxide insulator layer has at least one of a contoured top surface and a contoured bottom surface. Also provided are processes for manufacturing such a SOI wafer.
摘要翻译：绝缘体上硅晶片。 SOI晶片包括顶部硅层，硅衬底和跨过晶片设置在硅衬底和顶部硅层之间的氧化物绝缘体层。氧化物绝缘体层具有轮廓顶表面和轮廓底表面中的至少一个。还提供了用于制造这种SOI晶片的工艺。

5. 发明申请

US20100013044A1 THREE-DIMENSIONAL SILICON ON OXIDE DEVICE ISOLATION 有权
标题翻译：氧化物分离器上的三维硅
公开(公告)号：US20100013044A1
公开(公告)日：2010-01-21
申请号：US10596569
申请日：2003-12-16
申请人： Levent Gulari
发明人： Levent Gulari
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： B81C1/00507 , H01L21/76243 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).
摘要翻译：绝缘体上硅晶片（10）。 SOI晶片（10）包括顶部硅层（6），硅衬底（4）和跨过晶片（10）并且位于硅衬底（4）和顶部硅层之间的氧化物绝缘体层（2）（6）。氧化物绝缘体层（2）具有轮廓顶面（8a，8b，8c，8d，8e）和轮廓底面（12e）中的至少一个。还提供了用于制造这种SOI晶片（10）的工艺。

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