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1. 发明授权

US06992004B1 Implanted barrier layer to improve line reliability and method of forming same 有权
标题翻译：植入障碍层提高线路可靠性及其形成方法
公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译：用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。孔被金属材料填充，并且在金属材料上方设有阻挡层。可以在金属材料和阻挡层的界面处形成金属间化合物区域。金属间化合物可以通过种植物形成。

2. 发明授权

US07169706B2 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

3. 发明授权

US06518167B1 Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权
标题翻译：在氮化硅和铜之间形成金属或金属氮化物界面层的方法
公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译：在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

4. 发明授权

US06589408B1 Non-planar copper alloy target for plasma vapor deposition systems 有权
标题翻译：用于等离子体气相沉积系统的非平面铜合金靶
公开(公告)号：US06589408B1
公开(公告)日：2003-07-08
申请号：US10107778
申请日：2002-03-27
申请人： Pin-Chin Connie Wang , Paul R. Besser , Sergey D. Lopatin , Minh Q. Tran
发明人： Pin-Chin Connie Wang , Paul R. Besser , Sergey D. Lopatin , Minh Q. Tran
IPC分类号： C23C1435
CPC分类号： C23C14/3414 , C23C14/3407
摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.
摘要翻译：非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。侧面环形部分具有端部连接到顶部平面部分的端部。第一合金浓度和第二合金浓度不同。

5. 发明授权

US06979642B1 Method of self-annealing conductive lines that separates grain size effects from alloy mobility 有权
标题翻译：将晶粒尺寸效应与合金迁移率分离的导电线自退火方法
公开(公告)号：US06979642B1
公开(公告)日：2005-12-27
申请号：US10628733
申请日：2003-07-28
申请人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
发明人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
IPC分类号： H01L21/283 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/321 , H01L21/76877
摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.
摘要翻译：形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。合金元素可以减少与导电结构相关的电迁移问题。导电结构在较长时间内在低温过程中自退火或首先退火。利用另一退火来分配合金元素。

6. 发明授权

US08026169B2 Cu annealing for improved data retention in flash memory devices 有权
标题翻译： Cu退火以改善闪存器件中的数据保留
公开(公告)号：US08026169B2
公开(公告)日：2011-09-27
申请号：US11593086
申请日：2006-11-06
申请人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
发明人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
IPC分类号： H01L21/4763
CPC分类号： H01L21/76883 , H01L27/11521
摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
摘要翻译：通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。实施方案包括在含有低H 2或不含H 2的N 2气氛中以及在低于200℃，例如100℃至150℃的温度下退火镶嵌Cu。

7. 发明申请

US20080108193A1 Cu annealing for improved data retention in flash memory devices 有权
标题翻译： Cu退火以改善闪存器件中的数据保留
公开(公告)号：US20080108193A1
公开(公告)日：2008-05-08
申请号：US11593086
申请日：2006-11-06
申请人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
发明人： Lu You , Alexander Nickel , Minh Q. Tran , Minh-Van Ngo , Hieu Pham , Erik Wilson , Hirokazu Tokuno , Amir Hossein Jafarpour , Inkuk Kang , Robert Huertas
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/76883 , H01L27/11521
摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.
摘要翻译：通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu，例如，100℃至150℃

8. 发明授权

US08735960B2 High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance 有权
标题翻译：高紫外光吸收氧氮化硅薄膜，用于改善闪存器件性能
公开(公告)号：US08735960B2
公开(公告)日：2014-05-27
申请号：US12313134
申请日：2008-11-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L23/485 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
摘要翻译：紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

9. 发明授权

US08611035B1 Capacitance sensor for determining a distance between a head and a magnetic storage medium 有权
标题翻译：用于确定头部和磁性存储介质之间的距离的电容传感器
公开(公告)号：US08611035B1
公开(公告)日：2013-12-17
申请号：US13367334
申请日：2012-02-06
申请人： Sateeshchandra S. Bajikar , Minh Q. Tran
发明人： Sateeshchandra S. Bajikar , Minh Q. Tran
IPC分类号： G11B5/56
CPC分类号： G11B5/6017 , G11B19/042
摘要： A proximity sensor is described including a capacitor formed by a first conductive element and a second conductive element. The first conductive element and the second conductive element are situated at a magnetic head, a slider that connects to the magnetic head, a reader of the magnetic head, a writer of the magnetic head, a reader shield of the magnetic head, or a writer shield of the magnetic head. A capacitance and a fringing electric field are formed by the capacitor when there is a voltage difference between the first conductive element and the second conductive element. The capacitor is situated such that the fringing electric field changes with a positioning change of a magnetic storage medium with respect to at least one of the first conductive element and the second conductive element. The capacitor is also situated such that the capacitance changes with the fringing electric field change.
摘要翻译：描述了一种接近传感器，其包括由第一导电元件和第二导电元件形成的电容器。第一导电元件和第二导电元件位于磁头，连接到磁头的滑块，磁头的读取器，磁头的写入器，磁头的读取器屏蔽件或写入器屏蔽磁头。当第一导电元件和第二导电元件之间存在电压差时，由电容器形成电容和边缘电场。电容器设置成使得边缘电场相对于第一导电元件和第二导电元件中的至少一个的磁存储介质的定位变化而变化。电容器也被定位成使得电容随边缘电场变化而变化。

10. 发明授权

US08633074B2 Electrically programmable and erasable memory device and method of fabrication thereof 有权
标题翻译：电可编程和可擦除存储器件及其制造方法
公开(公告)号：US08633074B2
公开(公告)日：2014-01-21
申请号：US12284002
申请日：2008-09-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
IPC分类号： H01L21/336
CPC分类号： H01L29/7888 , H01L21/28282 , H01L27/11517 , H01L27/11563 , H01L29/513 , H01L29/792
摘要： The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
摘要翻译：本存储器件包括衬底，衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的电介质，并且包括氮氧化硅，以及在电介质上的控制栅极。还提供了一种用于制造这种存储器件的方法，包括用于形成氮氧化硅的各种方法。

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