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1. 发明授权

US06992004B1 Implanted barrier layer to improve line reliability and method of forming same 有权
标题翻译：植入障碍层提高线路可靠性及其形成方法
公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译：用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。孔被金属材料填充，并且在金属材料上方设有阻挡层。可以在金属材料和阻挡层的界面处形成金属间化合物区域。金属间化合物可以通过种植物形成。

2. 发明授权

US06518167B1 Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权
标题翻译：在氮化硅和铜之间形成金属或金属氮化物界面层的方法
公开(公告)号：US06518167B1
公开(公告)日：2003-02-11
申请号：US10123588
申请日：2002-04-16
申请人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
发明人： Lu You , Matthew S. Buynoski , Paul R. Besser , Jeremias D. Romero , Pin-Chin Connie Wang , Minh Q. Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/28562 , H01L21/76834
摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.
摘要翻译：在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

3. 发明授权

US06815340B1 Method of forming an electroless nucleation layer on a via bottom 有权
标题翻译：在通孔底部形成无电解成核层的方法
公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译：制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物，以及使用合金在导电层的暴露部分上形成成核层。成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

4. 发明授权

US06861349B1 Method of forming an adhesion layer with an element reactive with a barrier layer 失效
标题翻译：用与阻挡层反应的元件形成粘合层的方法
公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元素进入阻挡材料层上的界面层，在界面层上沉积合金层。植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

5. 发明授权

US06979642B1 Method of self-annealing conductive lines that separates grain size effects from alloy mobility 有权
标题翻译：将晶粒尺寸效应与合金迁移率分离的导电线自退火方法
公开(公告)号：US06979642B1
公开(公告)日：2005-12-27
申请号：US10628733
申请日：2003-07-28
申请人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
发明人： Matthew S. Buynoski , Connie Pin-Chin Wang , Paul R. Besser , Minh Q. Tran
IPC分类号： H01L21/283 , H01L21/288 , H01L21/321 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/321 , H01L21/76877
摘要： A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.
摘要翻译：形成诸如铜导电结构，管线或通孔的导电结构的方法被优化用于合金元件的大晶粒生长和分布。合金元素可以减少与导电结构相关的电迁移问题。导电结构在较长时间内在低温过程中自退火或首先退火。利用另一退火来分配合金元素。

6. 发明授权

US06724087B1 Laminated conductive lines and methods of forming the same 有权
标题翻译：层叠导电线及其形成方法
公开(公告)号：US06724087B1
公开(公告)日：2004-04-20
申请号：US10331682
申请日：2002-12-30
申请人： Matthew S. Buynoski , Paul R. Besser , Sergey D. Lopatin , Lu You
发明人： Matthew S. Buynoski , Paul R. Besser , Sergey D. Lopatin , Lu You
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76847 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at least one interconnect layer, the interconnect layer including a number of conductive lines. Each of the conductive lines includes a first thin barrier layer, a first thin copper layer, a second thin barrier layer and a second thin copper layer. The layered or laminated structure can reduce unconstrained void formation.
摘要翻译：集成电路的制造方法可以包括形成叠层导电线。层叠导电线可以形成在电介质沟槽中。层叠导电线可以包括交替的阻挡层和铜层。集成电路包括至少一个互连层，所述互连层包括多个导电线。每个导线包括第一薄势垒层，第一薄铜层，第二薄阻挡层和第二薄铜层。分层或层压结构可以减少无约束的空隙形成。

7. 发明授权

US06710452B1 Coherent diffusion barriers for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干扩散屏障
公开(公告)号：US06710452B1
公开(公告)日：2004-03-23
申请号：US09618964
申请日：2000-07-19
申请人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L21/76886 , H01L21/76888 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。阻挡层具有比通道介电层更加负的形成热量，由此阻挡层与导体芯的材料扩散到沟道介电层上形成阻挡层。阻挡层还与导体芯形成稳定的化合物，以形成将沟道电介质结合到导体芯的相干势垒层。

8. 发明授权

US06703307B2 Method of implantation after copper seed deposition 失效
标题翻译：铜种子沉积后植入方法
公开(公告)号：US06703307B2
公开(公告)日：2004-03-09
申请号：US09994358
申请日：2001-11-26
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76859 , H01L21/76867 , H01L21/76871
摘要： A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.
摘要翻译：制造集成电路的方法可以包括沿着横向侧壁和通孔孔的底部形成阻挡层，形成靠近并与保护层保持的种子层，以及在阻挡层附近形成注入层，种子层。通孔被配置为接收电连接第一导电层和第二导电层的通孔材料。

9. 发明授权

US06583012B1 Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes 有权
标题翻译：利用不同组合的金属基嵌入栅电极的半导体器件
公开(公告)号：US06583012B1
公开(公告)日：2003-06-24
申请号：US09781436
申请日：2001-02-13
申请人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
发明人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
IPC分类号： H01L218234
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28518 , H01L21/823842
摘要： MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP. The invention also includes MOS and CMOS devices comprising differently composed in-laid, metal-based gate electrodes.
摘要翻译：包括多个晶体管的MOS晶体管和CMOS器件包括具有不同组成的嵌入式金属基栅极的多个晶体管，其特征在于，包括：在绝缘层的底部沉积第一金属填充开口的第一覆盖层，形成在半导体衬底中的MOS晶体管前体区的开口栅极绝缘体层段露出; 选择性地形成覆盖所选择的MOS晶体管前体区域的第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或硅的第二覆盖层，并且在覆盖其它MOS晶体管前体区域的第一和第二覆盖层的接触部分之间进行合金化或硅化反应。然后通过进行平坦化处理，例如通过CMP除去在合金化或硅化反应之后残留的不必要的层。本发明还包括包括不同组合的嵌入式金属基栅极的MOS和CMOS器件。

10. 发明授权

US06559051B1 Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积
公开(公告)号：US06559051B1
公开(公告)日：2003-05-06
申请号：US09679881
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
发明人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应的半导体衬底以形成至少一种金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

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