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1. 发明授权

US07169706B2 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

2. 发明授权

US06703308B1 Method of inserting alloy elements to reduce copper diffusion and bulk diffusion 失效
标题翻译：插入合金元素以减少铜扩散和体扩散的方法
公开(公告)号：US06703308B1
公开(公告)日：2004-03-09
申请号：US09994400
申请日：2001-11-26
申请人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
发明人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76859 , H01L21/76867
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

3. 发明授权

US06791081B1 Method for determining pore characteristics in porous materials 失效
标题翻译：确定多孔材料孔隙特性的方法
公开(公告)号：US06791081B1
公开(公告)日：2004-09-14
申请号：US10109517
申请日：2002-03-27
申请人： Robert Matthew Ulfig , Suzette K. Pangrle , Alline F. Myers , Jeremias D. Romero
发明人： Robert Matthew Ulfig , Suzette K. Pangrle , Alline F. Myers , Jeremias D. Romero
IPC分类号： G01B528
CPC分类号： G01Q60/24 , G01N15/088 , Y10S977/852
摘要： A method for measuring porosity of nanoporous materials is provided using atomic force microscopy (AFM). A surface topology map with sub-atomic resolution is created using AFM wherein the pore shape and size can be determined by measuring the pores that intersect the top or fracture surface. For porous materials requiring more accurate measurements, small scan areas with slow scan speed and fine AFM tips are used and a general estimation on distribution can be made from a sample area.
摘要翻译：使用原子力显微镜（AFM）提供了一种测量纳米多孔材料孔隙率的方法。使用AFM创建具有亚原子分辨率的表面拓扑图，其中孔形状和尺寸可以通过测量与顶部或断裂面相交的孔来确定。对于需要更精确测量的多孔材料，使用扫描速度慢的微小扫描区域和精细的AFM尖端，并且可以从样品区域进行一般的分布估计。

4. 发明授权

US06500754B1 Anneal hillock suppression method in integrated circuit interconnects 有权
标题翻译：集成电路互连中的退火小丘抑制方法
公开(公告)号：US06500754B1
公开(公告)日：2002-12-31
申请号：US09999661
申请日：2001-10-31
申请人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
发明人： Darrell M. Erb , Steven C. Avanzino , Alline F. Myers
IPC分类号： H01L214763
CPC分类号： H01L21/76883
摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. Before planarization of the conductor core and the barrier layer, an anneal of the semiconductor substrate is performed at high temperatures of 400° C. and above to stimulate grain growth. After planarization, subsequent high temperature deposition of passivating or capping layers will not cause grain growth and hillocks will be suppressed.
摘要翻译：因此，提供了具有半导体器件的半导体衬底的集成电路和制造方法。在半导体基板上形成器件电介质层，在器件电介质层上形成的沟道电介质层形成有开口部。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。在导体芯和阻挡层平坦化之前，在400℃及以上的高温下进行半导体衬底的退火以刺激晶粒生长。在平坦化之后，随后的钝化层或覆盖层的高温沉积将不会导致晶粒生长并且抑制小丘。

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