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1. 发明申请

US20100123178A1 High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance 有权
标题翻译：高紫外光吸收氧氮化硅薄膜，用于改善闪存器件性能
公开(公告)号：US20100123178A1
公开(公告)日：2010-05-20
申请号：US12313134
申请日：2008-11-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L23/485 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
摘要翻译：紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

2. 发明授权

US08735960B2 High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance 有权
标题翻译：高紫外光吸收氧氮化硅薄膜，用于改善闪存器件性能
公开(公告)号：US08735960B2
公开(公告)日：2014-05-27
申请号：US12313134
申请日：2008-11-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L23/485 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
摘要翻译：紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

3. 发明授权

US08633074B2 Electrically programmable and erasable memory device and method of fabrication thereof 有权
标题翻译：电可编程和可擦除存储器件及其制造方法
公开(公告)号：US08633074B2
公开(公告)日：2014-01-21
申请号：US12284002
申请日：2008-09-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
IPC分类号： H01L21/336
CPC分类号： H01L29/7888 , H01L21/28282 , H01L27/11517 , H01L27/11563 , H01L29/513 , H01L29/792
摘要： The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
摘要翻译：本存储器件包括衬底，衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的电介质，并且包括氮氧化硅，以及在电介质上的控制栅极。还提供了一种用于制造这种存储器件的方法，包括用于形成氮氧化硅的各种方法。

4. 发明申请

US20100065901A1 Electrically programmable and erasable memory device and method of fabrication thereof 有权
标题翻译：电可编程和可擦除存储器件及其制造方法
公开(公告)号：US20100065901A1
公开(公告)日：2010-03-18
申请号：US12284002
申请日：2008-09-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Jeong-Uk Huh
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/7888 , H01L21/28282 , H01L27/11517 , H01L27/11563 , H01L29/513 , H01L29/792
摘要： The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.
摘要翻译：本存储器件包括衬底，衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的电介质，并且包括氮氧化硅，以及在电介质上的控制栅极。还提供了一种用于制造这种存储器件的方法，包括用于形成氮氧化硅的各种方法。

5. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

6. 发明申请

US20090176369A1 LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES 有权
标题翻译：用于电子存储器件的N2天线的低等离子体处理
公开(公告)号：US20090176369A1
公开(公告)日：2009-07-09
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

7. 发明授权

US06515368B1 Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper 有权
标题翻译：具有铜填充通孔的半导体器件包括用于减少铜的电迁移的铜 - 锌/合金膜
公开(公告)号：US06515368B1
公开(公告)日：2003-02-04
申请号：US10016410
申请日：2001-12-07
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： H01L23532
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76846 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.
摘要翻译：一种通过在铜（Cu）表面上电镀铜离子铜（Cu）的中间铜 - 锌合金（Cu-Zn）薄膜上，通过用Zn掺杂Cu表面来限制沿Cu表面的Cu扩散路径来减少铜互连线中的电迁移的方法稳定的化学溶液，并且控制其Zn掺杂，这也提高了互连可靠性和耐腐蚀性，以及由此形成的半导体器件。该方法包括使用临时还原氧Cu-Zn合金薄膜来形成封装的双镶嵌互连结构。通过电镀电镀Cu表面，通过电镀Cu晶体，以独特的含有Zn和Cu盐的化学溶液，它们的络合剂，pH调节剂和表面活性剂形成Cu表面; 并对中间电镀Cu-Zn合金薄膜和Cu填充进行退火; 并平坦化互连结构。

8. 发明申请

US20140061714A1 P-N SEPARATION METAL FILL FOR FLIP CHIP LEDS 有权
标题翻译： P-N分离金属填充片
公开(公告)号：US20140061714A1
公开(公告)日：2014-03-06
申请号：US14112279
申请日：2012-04-25
申请人： Jipu Lei , Yajun Wei , Alexander H. Nickel , Stefano Schiafino , Daniel Alexander Steigerwald
发明人： Jipu Lei , Yajun Wei , Alexander H. Nickel , Stefano Schiafino , Daniel Alexander Steigerwald
IPC分类号： H01L33/62 , H01L33/00
CPC分类号： H01L33/62 , H01L24/13 , H01L24/14 , H01L33/005 , H01L33/0079 , H01L33/486 , H01L2224/13008 , H01L2224/13022 , H01L2224/13144 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2924/01019 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2933/0066 , H01L2924/00014 , H01L2924/00
摘要： A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semi-conductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
摘要翻译：发光二极管（LED）结构（10）具有半导体层，包括p型层，有源层和n型层。 p型层具有底面，n型层具有发射光的顶面。蚀刻p型层和有源层的部分以露出n型层。 LED的表面用光致抗蚀剂图案化，并且将铜电镀在暴露的表面上，以形成与其相应的半导体层电接触的p和n电极。 n和p电极之间有间隙。为了在间隙之间提供半导体层的机械支撑，在间隙中形成介电层（34），随后用金属（42）填充间隙。金属被图案化以形成基本上覆盖LED管芯的底表面但不会使电极短路的螺柱凸块（40,42,44）。基本均匀的覆盖在后续工艺步骤中支持半导体层。

9. 发明授权

US06528424B1 Method of electroplating a copper-zinc alloy thin film on a copper surface using a chemical solution 有权
标题翻译：使用化学溶液在铜表面上电镀铜锌合金薄膜的方法
公开(公告)号：US06528424B1
公开(公告)日：2003-03-04
申请号：US10082432
申请日：2002-02-22
申请人： Sergey Lopatin , Alexander H. Nickel
发明人： Sergey Lopatin , Alexander H. Nickel
IPC分类号： H01L2144
CPC分类号： H01L21/7685 , C25D3/58 , C25D5/18 , C25D7/12 , C25D17/001 , H01L21/2885
摘要： A method of fabricating a semiconductor device, having a Cu-rich Cu—Zn alloy thin film (30) formed on a cathode-wafer such as a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform Cu-rich Cu—Zn alloy thin film (30) for reducing electromigration on the cathode-wafer by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.
摘要翻译：一种制造半导体器件的方法，所述半导体器件具有通过使用电镀设备在所述Cu表面（20）的阴极晶片（20）上形成的富Cu Cu-Zn合金薄膜（30），所述Cu表面（20）在含有锌（Zn）和铜（Cu）的盐，其络合剂，pH调节剂和表面活性剂的独特的化学溶液中; 并由此形成半导体器件。该方法控制pH，温度和时间的参数，以形成均匀的富Cu Cu-Zn合金薄膜（30），用于通过降低其中的漂移速度来减小阴极晶片上的电迁移，从而降低Cu迁移率除了降低空隙形成速率，提高装置的可靠性和提高耐腐蚀性之外，

10. 发明授权

US09219209B2 P-N separation metal fill for flip chip LEDs 有权
标题翻译： P-N分离金属填充倒装芯片LED
公开(公告)号：US09219209B2
公开(公告)日：2015-12-22
申请号：US14112279
申请日：2012-04-25
申请人： Jipu Lei , Yajun Wei , Alexander H. Nickel , Stefano Schiafino , Daniel Alexander Steigerwald
发明人： Jipu Lei , Yajun Wei , Alexander H. Nickel , Stefano Schiafino , Daniel Alexander Steigerwald
IPC分类号： H01L33/62 , H01L33/00 , H01L33/48 , H01L23/00
CPC分类号： H01L33/62 , H01L24/13 , H01L24/14 , H01L33/005 , H01L33/0079 , H01L33/486 , H01L2224/13008 , H01L2224/13022 , H01L2224/13144 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2924/01019 , H01L2924/12041 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , H01L2933/0066 , H01L2924/00014 , H01L2924/00
摘要： A light emitting diode (LED) structure (10) has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer (34) is formed in the gap followed by filling the gap with a metal (42). The metal is patterned to form stud bumps (40, 42, 44) that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.
摘要翻译：发光二极管（LED）结构（10）具有半导体层，包括p型层，有源层和n型层。 p型层具有底面，n型层具有发射光的顶面。蚀刻p型层和有源层的部分以露出n型层。 LED的表面用光致抗蚀剂图案化，并且铜暴露在暴露的表面上以形成与其各自的半导体层电接触的p和n电极。 n和p电极之间有间隙。为了在间隙之间提供半导体层的机械支撑，在间隙中形成介电层（34），随后用金属（42）填充间隙。金属被图案化以形成基本上覆盖LED管芯的底表面但不会使电极短路的螺柱凸块（40,42,44）。基本均匀的覆盖在后续工艺步骤中支持半导体层。

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