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1. 发明授权

US08127118B2 Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays 失效
标题翻译：微结构，方法和计算机程序产品，用于从一组跟踪数组收集高效数据
公开(公告)号：US08127118B2
公开(公告)日：2012-02-28
申请号：US12036540
申请日：2008-02-25
申请人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
发明人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
IPC分类号： G06F9/00 , G06F11/00
CPC分类号： G06F11/3466
摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.
摘要翻译：一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。提供了一种方法和计算机程序产品。

2. 发明申请

US20090217012A1 MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS 失效
标题翻译：微观研究，方法和计算机程序产品，用于从一组跟踪阵列高效数据收集
公开(公告)号：US20090217012A1
公开(公告)日：2009-08-27
申请号：US12036540
申请日：2008-02-25
申请人： Patrick M. West, JR. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
发明人： Patrick M. West, JR. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
IPC分类号： G06F9/22
CPC分类号： G06F11/3466
摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.
摘要翻译：一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。提供了一种方法和计算机程序产品。

3. 发明授权

US07870438B2 Method, system and computer program product for sampling computer system performance data 失效
标题翻译：方法，系统和计算机程序产品，用于对计算机系统性能数据进行采样
公开(公告)号：US07870438B2
公开(公告)日：2011-01-11
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, Jr.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译：提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。响应于将仪器数据存储在采样缓冲器中，取样中断被置位。

4. 发明申请

US20090210752A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA 失效
标题翻译：用于采样计算机系统性能数据的方法，系统和计算机程序产品
公开(公告)号：US20090210752A1
公开(公告)日：2009-08-20
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译：提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。响应于将仪器数据存储在采样缓冲器中，取样中断被置位。

5. 发明授权

US07200742B2 System and method for creating precise exceptions 失效
标题翻译：用于创建精确异常的系统和方法
公开(公告)号：US07200742B2
公开(公告)日：2007-04-03
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
IPC分类号： G06F9/38
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译：一种用于创建精确异常的方法，包括检查指向引起异常的指令。检查点导致当前检查点状态。当前检查点状态被锁定。确定多个寄存器中的任一个是否需要恢复到当前检查点状态。响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

6. 发明申请

US20120278548A1 OPTIMIZING EDRAM REFRESH RATES IN A HIGH PERFORMANCE CACHE ARCHITECTURE 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US20120278548A1
公开(公告)日：2012-11-01
申请号：US13546687
申请日：2012-07-11
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, JR. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, JR. , Scott B. Swaney
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Optimizing EDRAM refresh rates in a high performance cache architecture. An aspect of the invention includes receiving a plurality of first signals. A refresh request is transmitted via a refresh requestor to a cache memory at a first refresh rate which includes an interval, including a subset of the first signals. The first refresh rate corresponds to a maximum refresh rate. A refresh counter is reset based on receiving a second signal. The refresh counter is incremented after receiving each of a number of refresh requests. A current count is transmitted from a refresh counter to the refresh requestor based on receiving a third signal. The refresh request is transmitted at a second refresh rate, which is less than the first refresh rate. The refresh request is transmitted based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：在高性能缓存架构中优化EDRAM刷新率。本发明的一个方面包括接收多个第一信号。经由刷新请求者的刷新请求以包括包括第一信号的子集的间隔的第一刷新率被发送到高速缓冲存储器。第一个刷新率对应于最大刷新率。基于接收到第二信号，刷新计数器被复位。刷新计数器在接收到多个刷新请求之后递增。基于接收到第三信号，从刷新计数器向刷新请求者发送当前计数。刷新请求以小于第一刷新率的第二刷新率发送。基于从刷新计数器接收当前计数并确定当前计数大于刷新阈值来发送刷新请求。

7. 发明授权

US09164761B2 Obtaining data in a pipelined processor 有权
标题翻译：在流水线处理器中获取数据
公开(公告)号：US09164761B2
公开(公告)日：2015-10-20
申请号：US12033351
申请日：2008-02-19
申请人： Aaron Tsai , Bruce C. Giamei , Chung-Lung Kevin Shum , Scott B. Swaney
发明人： Aaron Tsai , Bruce C. Giamei , Chung-Lung Kevin Shum , Scott B. Swaney
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/3879
摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.
摘要翻译：流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。特殊指令的执行在相应的单位启动。如果执行特殊指令的单元不是LSU，则将数据发送到LSU。作为执行特殊指令的结果，从LSU接收数据。数据被提供给请求者。

8. 发明申请

US20090206872A1 SYSTEM, METHOD AND APPARATUS FOR ENHANCING RELIABILITY ON SCAN-INITIALIZED LATCHES AFFECTING FUNCTIONALITY 有权
标题翻译：系统，方法和装置，用于增强影响功能的扫描初始化锁存器的可靠性
公开(公告)号：US20090206872A1
公开(公告)日：2009-08-20
申请号：US12031730
申请日：2008-02-15
申请人： Chung-Lung Kevin Shum , Scott B. Swaney
发明人： Chung-Lung Kevin Shum , Scott B. Swaney
IPC分类号： H03K19/003
CPC分类号： H03K19/0033
摘要： A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches, where the latches are scan initialized. The system also includes a disable allowance latch (DAL) allocated to the group of latches, where the DAL is a scan-initialized latch. The system further includes a gating function outputting the state value of at least one of the latches in the group to a functional block in the digital design in response to the DAL being in an enabled state and blocking the gating function output in response to the DAL being in a disabled state.
摘要翻译：提供了一种用于提高影响数字设计中的功能的扫描初始化锁存器的可靠性的系统，方法和装置。该系统包括一组锁存器，其基于锁存器的状态值影响数字设计中的功能，其中锁存器被扫描初始化。该系统还包括分配给锁存器组的禁用允许锁存器（DAL），其中DAL是扫描初始化的锁存器。该系统还包括选通功能，以响应于DAL处于使能状态，将组中的至少一个锁存器的状态值输出到数字设计中的功能块，并响应于DAL阻塞门控功能输出处于残疾状态。

9. 发明授权

US07343534B2 Method for deferred data collection in a clock running system 有权
标题翻译：时钟运行系统中延迟数据采集的方法
公开(公告)号：US07343534B2
公开(公告)日：2008-03-11
申请号：US10855047
申请日：2004-05-27
申请人： Patrick J. Meaney , Kurt A. Grassmann , Oliver Marquardt , Scott B. Swaney
发明人： Patrick J. Meaney , Kurt A. Grassmann , Oliver Marquardt , Scott B. Swaney
IPC分类号： G11F29/00
CPC分类号： G06F11/3636 , G06F11/0724 , G06F11/0772 , G06F11/0778
摘要： A method for deferred logging of machine data following an error or event in order to capture critical information for that error or event treats the data as persistent and it does not get logged until a disruption occurs to the system (e.g. system reset, restart, deactivation, or powered-down). This way, important debug data can be held in the hardware or software, without a need for complicated hardware and code for logging this debug data. Methods are also disclosed for setting a switch to indicate deferred logging is required, referencing the log data with the original event information, calling home with the debug data, resetting the deferred logging switch, setting the deferred logging switch manually, viewing whether the switch is already set, and supporting different kinds of switches.
摘要翻译：在错误或事件之后延迟记录机器数据以便捕获该错误或事件的关键信息的方法将数据视为持久性，并且在系统发生中断之前不会记录数据（例如系统复位，重新启动，停用，或掉电）。这样，重要的调试数据可以在硬件或软件中保存，而无需复杂的硬件和代码来记录调试数据。还公开了设置交换机以指示延迟日志记录的方法，参考具有原始事件信息的日志数据，使用调试数据调用主机，重新设置延迟记录交换机，手动设置延迟记录交换机，查看交换机是否已经设置，并支持不同种类的交换机。

10. 发明授权

US07777520B2 System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality 有权
标题翻译：用于增强影响功能的扫描初始化锁存器的可靠性的系统，方法和装置
公开(公告)号：US07777520B2
公开(公告)日：2010-08-17
申请号：US12031730
申请日：2008-02-15
申请人： Chung-Lung Kevin Shum , Scott B. Swaney
发明人： Chung-Lung Kevin Shum , Scott B. Swaney
IPC分类号： H03K19/173
CPC分类号： H03K19/0033
摘要： A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches, where the latches are scan initialized. The system also includes a disable allowance latch (DAL) allocated to the group of latches, where the DAL is a scan-initialized latch. The system further includes a gating function outputting the state value of at least one of the latches in the group to a functional block in the digital design in response to the DAL being in an enabled state and blocking the gating function output in response to the DAL being in a disabled state.
摘要翻译：提供了一种用于提高影响数字设计中的功能的扫描初始化锁存器的可靠性的系统，方法和装置。该系统包括一组锁存器，其基于锁存器的状态值影响数字设计中的功能，其中锁存器被扫描初始化。该系统还包括分配给锁存器组的禁用允许锁存器（DAL），其中DAL是扫描初始化的锁存器。该系统还包括选通功能，以响应于DAL处于使能状态，将组中的至少一个锁存器的状态值输出到数字设计中的功能块，并响应于DAL阻塞门控功能输出处于残疾状态。

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