专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07200742B2 System and method for creating precise exceptions 失效
标题翻译：用于创建精确异常的系统和方法
公开(公告)号：US07200742B2
公开(公告)日：2007-04-03
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
IPC分类号： G06F9/38
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译：一种用于创建精确异常的方法，包括检查指向引起异常的指令。检查点导致当前检查点状态。当前检查点状态被锁定。确定多个寄存器中的任一个是否需要恢复到当前检查点状态。响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

2. 发明授权

US07490121B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07490121B2
公开(公告)日：2009-02-10
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

3. 发明授权

US07853635B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07853635B2
公开(公告)日：2010-12-14
申请号：US11749224
申请日：2007-05-16
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.
摘要翻译：超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

4. 发明授权

US07266580B2 Modular binary multiplier for signed and unsigned operands of variable widths 有权
标题翻译：具有可变宽度的有符号和无符号操作数的模块二进制乘法器
公开(公告)号：US07266580B2
公开(公告)日：2007-09-04
申请号：US10435976
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Steven R. Carlough , David S. Hutton , Christopher A. Krygowski , John G. Rell, Jr. , Sheryll H. Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.
摘要翻译：本文中讨论了用于对具有各种长度的有符号和无符号操作数进行二进制乘法的方法和装置。这是一个概念，可以分为两部分，第一部分是乘法硬件本身，紧凑型，小于满量程的乘法器，在乘数上使用Booth或其他类型的重新编码方法，以减少每个部分产品的数量扫描和实现，使得具有大操作数的乘法运算可以被分解成适合于该中型乘法器的操作子组，其结果（这里称为模块化产品）可以针织在一起以形成正确的，完成品。该概念的第二部分是用于将操作数分成子组并将数据和控制信号输入到乘法器的支持硬件，以及用于对准和组合模块化产品以获得最终产品的算法和装置。用于获得由操作指定的结果的这些算法可以与可以使用乘法器的支持硬件一样变化，使得该乘法器是非常灵活和强大的设计。

5. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

6. 发明授权

US07085917B2 Multi-pipe dispatch and execution of complex instructions in a superscalar processor 有权
标题翻译：超标量处理器中的多管调度和复杂指令的执行
公开(公告)号：US07085917B2
公开(公告)日：2006-08-01
申请号：US10435983
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/325 , G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invention allows multi-cycle and complex instructions to be dispatched to one port but executed in multiple execution pipes without cracking the instruction and without limiting it to a single execution pipe. Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). The FXU logic then execute these instructions on the available FXU pipes. This method results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译：在计算机系统中，用于调度和执行多周期和复杂指令的方法和装置。该方法导致最大的性能，而不会影响处理器中的其他区域，如解码，分组或调度单元。本发明允许将多周期和复杂指令分派到一个端口，但是在多个执行管道中执行，而不会破坏指令，而不限于单个执行管道。在调度单元中生成一些控制信号，并通过指令发送到定点单元（FXU）。然后，FXU逻辑在可用的FXU管道上执行这些说明。这种方法导致最佳性能，很少或没有其他并发症。所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。

7. 发明授权

US07921279B2 Operand and result forwarding between differently sized operands in a superscalar processor 失效
标题翻译：操作数和结果在超标量处理器中的不同大小的操作数之间转发
公开(公告)号：US07921279B2
公开(公告)日：2011-04-05
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, Jr. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

8. 发明授权

US07913067B2 Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor 失效
标题翻译：用于通过按顺序处理器中的非均匀执行流水线重复执行指令的方法和系统
公开(公告)号：US07913067B2
公开(公告)日：2011-03-22
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

9. 发明申请

US20090210656A1 METHOD AND SYSTEM FOR OVERLAPPING EXECUTION OF INSTRUCTIONS THROUGH NON-UNIFORM EXECUTION PIPELINES IN AN IN-ORDER PROCESSOR 失效
标题翻译：通过非订单执行管理员在订单处理程序中执行指令的方法和系统
公开(公告)号：US20090210656A1
公开(公告)日：2009-08-20
申请号：US12034084
申请日：2008-02-20
申请人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： David S. Hutton , Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , John G. Rell, JR. , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F15/76 , G06F9/02 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/3857 , G06F9/3873
摘要： A system and method for overlapping execution (OE) of instructions through non-uniform execution pipelines in an in-order processor are provided. The system includes a first execution unit to perform instruction execution in a first execution pipeline. The system also includes a second execution unit to perform instruction execution in a second execution pipeline, where the second execution pipeline includes a greater number of stages than the first execution pipeline. The system further includes an instruction dispatch unit (IDU), the IDU including OE registers and logic for dispatching an OE-capable instruction to the first execution unit such that the instruction completes execution prior to completing execution of a previously dispatched instruction to the second execution unit. The system additionally includes a latch to hold a result of the execution of the OE-capable instruction until after the second execution unit completes the execution of the previously dispatched instruction.
摘要翻译：提供了一种用于通过在顺序处理器中的非均匀执行管线来重复执行（OE）指令的系统和方法。该系统包括在第一执行流水线中执行指令执行的第一执行单元。该系统还包括第二执行单元，用于在第二执行流水线中执行指令执行，其中第二执行流水线包括比第一执行流水线更多的级数。该系统还包括一个指令调度单元（IDU），该IDU包括OE寄存器和用于向第一执行单元分配一个OE能力指令的逻辑，使得指令在完成先前发送的指令执行之前完成执行单元。该系统还包括一个锁存器，用于保持执行OE能力指令的结果，直到第二执行单元完成先前发送的指令的执行。

10. 发明授权

US09280398B2 Major branch instructions 有权
公开(公告)号：US09280398B2
公开(公告)日：2016-03-08
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/52 , G06F9/38 , G06F9/32
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式