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1. 发明授权

US07254157B1 Method and apparatus for generating a phase locked spread spectrum clock signal 有权
标题翻译：用于产生锁相扩频时钟信号的方法和装置
公开(公告)号：US07254157B1
公开(公告)日：2007-08-07
申请号：US10109130
申请日：2002-03-27
申请人： Patrick J. Crotty , Austin H. Lesea
发明人： Patrick J. Crotty , Austin H. Lesea
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H03K3/84
摘要： A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.
摘要翻译：提供了一种在集成电路上产生扩频时钟信号的方法和装置。可以通过改变环形振荡器的电源电压来调制由环形振荡器产生的目标频率，从而改变目标频率。在一个实施例中，电源电压由可被数字控制的模拟多路复用器产生。固定电压源可以向模拟多路复用器提供输入信号。在一个实施例中，固定电压源可以用单位增益放大器来实现。

2. 发明授权

US07088172B1 Configurable voltage bias circuit for controlling buffer delays 有权
标题翻译：用于控制缓冲器延迟的可配置电压偏置电路
公开(公告)号：US07088172B1
公开(公告)日：2006-08-08
申请号：US10360465
申请日：2003-02-06
申请人： Austin H. Lesea , Patrick J. Crotty
发明人： Austin H. Lesea , Patrick J. Crotty
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/205
摘要： A configurable voltage bias circuit is used to control gate delays in buffers by adjusting the supply voltage of the buffers. The programmable voltage bias circuit includes a configurable voltage divider, which receives an input supply voltage and generates an output supply voltage, and a configurable resistance circuit, which is coupled between the configurable voltage divider and ground. By using a temperature dependent reference voltage to generate the input supply voltage, the output supply voltage is also made to be dependent upon temperature. The programmable voltage bias circuit of the present invention uses the temperature dependence of the output supply voltage to make the gate delays of the buffer temperature-independent.
摘要翻译：可配置的电压偏置电路用于通过调节缓冲器的电源电压来控制缓冲器中的栅极延迟。可编程电压偏置电路包括可配置的分压器，其接收输入电源电压并产生输出电源电压，以及耦合在可配置分压器和地之间的可配置电阻电路。通过使用与温度相关的参考电压来产生输入电源电压，输出电源电压也取决于温度。本发明的可编程电压偏置电路使用输出电源电压的温度依赖性使缓冲器的栅极延迟与温度无关。

3. 发明授权

US07853811B1 Suspend mode operation for reduced power 有权
标题翻译：挂起模式操作降低功耗
公开(公告)号：US07853811B1
公开(公告)日：2010-12-14
申请号：US11498467
申请日：2006-08-03
申请人： James A. Walstrum, Jr. , Mark A. Moran , Jinsong Oliver Huang , Patrick J. Crotty
发明人： James A. Walstrum, Jr. , Mark A. Moran , Jinsong Oliver Huang , Patrick J. Crotty
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.
摘要翻译：集成电路（300）包括一个挂起电路，该暂停电路包括用于接收暂停信号的第一输入端，产生唤醒信号的第一输出端，并输出以向各种集成电路资源提供控制信号。在暂停模式期间，暂停电路通过将其输出引脚驱动到由相应的模式选择信号选择的多个预定状态中的一个并通过将其同步元件锁定到已知状态来暂停集成电路资源的操作。在暂停模式终止时，电路根据用户定义的定时调度重新激活集成电路资源。用户定义的定时计划和模式选择信号可以在其配置期间被提供给集成电路，作为配置比特流的一部分。

4. 发明授权

US07046034B2 Programmable logic device having heterogeneous programmable logic blocks 有权
标题翻译：具有异构可编程逻辑块的可编程逻辑器件
公开(公告)号：US07046034B2
公开(公告)日：2006-05-16
申请号：US11144901
申请日：2005-06-03
申请人： Patrick J. Crotty , Tao Pi
发明人： Patrick J. Crotty , Tao Pi
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.
摘要翻译：具有异构可编程逻辑块的可编程逻辑器件（PLD）。在一个实施例中，PLD包括耦合到可编程互连电路的可编程互连电路和可编程输入 - 输出电路。可编程逻辑块的阵列耦合到互连电路。每个可编程逻辑块包括耦合到互连电路的多个可编程逻辑元件。每个可编程逻辑元件都是可编程的，以实现一组共同的功能，并且可编程逻辑元件中的至少一个但不是全部可编程以实现一组补充功能。

5. 发明授权

US06847246B1 Method and apparatus for reducing jitter and power dissipation in a delay line 有权
标题翻译：用于减少延迟线中的抖动和功耗的方法和装置
公开(公告)号：US06847246B1
公开(公告)日：2005-01-25
申请号：US10284725
申请日：2002-10-31
申请人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
发明人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.
摘要翻译：描述了用于降低延迟线中的功耗和抖动的方法和装置。延迟线包括多个延迟元件。多个延迟元件中的至少一个包括被配置为接收用于激活或去激活一个或多个延迟元件的栅极控制信号的栅极端子。延迟线还包括用于向多个延迟元件中的至少一个延迟元件的栅极端子提供栅极控制信号的栅极控制电路。

6. 发明授权

US06664807B1 Repeater for buffering a signal on a long data line of a programmable logic device 有权
标题翻译：用于在可编程逻辑器件的长数据线上缓冲信号的中继器
公开(公告)号：US06664807B1
公开(公告)日：2003-12-16
申请号：US10056724
申请日：2002-01-22
申请人： Patrick J. Crotty , Jinsong Oliver Huang
发明人： Patrick J. Crotty , Jinsong Oliver Huang
IPC分类号： H03K19177
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , H03K19/1776
摘要： A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.
摘要翻译：用于可编程逻辑器件的配置存储器阵列包括以行和列布置的配置存储器单元的阵列。最初，每个配置存储单元被复位到复位状态。配置存储单元的每一行都耦合到相应的数据线和数据线驱动器。在配置期间，每个数据线驱动器将具有第一状态或第二状态的配置数据值驱动到相应的数据线上。具有第一状态的配置数据值具有趋向于翻转配置存储单元的复位状态的极性。中继器单元连接到每个数据线的中间位置。每个中继器单元改进具有第一状态的配置数据值的驱动。

7. 发明授权

US6078201A Power-on reset circuit for dual supply voltages 失效
标题翻译：用于双电源电压的上电复位电路
公开(公告)号：US6078201A
公开(公告)日：2000-06-20
申请号：US3474
申请日：1998-01-06
申请人： Patrick J. Crotty
发明人： Patrick J. Crotty
IPC分类号： H03K17/22 , H03L7/00
CPC分类号： H03K17/223
摘要： A power-on reset circuit is provided which uses a dual voltage detection circuit to output a voltage detection signal. The dual voltage detection circuit is coupled to a first supply voltage terminal, a second supply voltage terminal, and a ground terminal. The voltage detection signal indicates whether the first supply voltage provided on the first supply voltage terminal is greater than an adequate voltage level. Furthermore, the voltage detection signal is driven by circuits powered by a second supply voltage provided on the second supply voltage terminal. One embodiment of the dual-voltage detection circuit comprises a first transistor coupled in series with a second transistor between the first supply voltage terminal and the ground terminal, as well as a third transistor coupled in series with a fourth transistor between the second supply voltage terminal and the ground terminal. Furthermore, some embodiments of the present invention also include a low pass filter coupled to the dual-voltage detection circuit to prevent spurious noise and ground bounces from causing a reset.
摘要翻译：提供了一种使用双电压检测电路输出电压检测信号的上电复位电路。双电压检测电路耦合到第一电源电压端子，第二电源电压端子和接地端子。电压检测信号指示提供在第一电源电压端子上的第一电源电压是否大于足够的电压电平。此外，电压检测信号由由设置在第二电源电压端子上的第二电源电压供电的电路驱动。双电压检测电路的一个实施例包括与第一电源电压端子和接地端子之间的第二晶体管串联耦合的第一晶体管，以及与第二电源电压端子之间的第四晶体管串联耦合的第三晶体管和地面终端。此外，本发明的一些实施例还包括耦合到双电压检测电路的低通滤波器，以防止杂散噪声和接地反弹引起复位。

8. 发明授权

US08503264B1 Reducing power consumption in a segmented memory 有权
标题翻译：降低分段存储器中的功耗
公开(公告)号：US08503264B1
公开(公告)日：2013-08-06
申请号：US13300512
申请日：2011-11-18
申请人： Sridhar Narayanan , Sridhar Subramanian , Matthew H. Klein , Patrick J. Crotty
发明人： Sridhar Narayanan , Sridhar Subramanian , Matthew H. Klein , Patrick J. Crotty
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory structure can include a first memory block including a plurality of memory cells corresponding to a first subset of addresses of a range of addresses and a second memory block including a plurality of memory cells corresponding to a second subset of addresses of the range of addresses. The memory structure can include control circuitry coupled to the first memory block and the second memory block and configured to provide control signals to the first memory block and the second memory block. The first memory block and the second memory block can be configured to implement a reduced power mode independently of one another responsive to the control signals.
摘要翻译：存储器结构可以包括第一存储器块，其包括对应于地址范围的地址的第一子集的多个存储器单元和包括对应于地址范围的地址的第二子集的多个存储器单元的第二存储器块。存储器结构可以包括耦合到第一存储器块和第二存储器块并被配置为向第一存储器块和第二存储器块提供控制信号的控制电路。第一存储器块和第二存储器块可以被配置为响应于控制信号彼此独立地实现降低功率模式。

9. 发明授权

US06667635B1 FPGA lookup table with transmission gate structure for reliable low-voltage operation 有权
标题翻译：具有传输门结构的FPGA查找表，可靠的低电压工作
公开(公告)号：US06667635B1
公开(公告)日：2003-12-23
申请号：US10241094
申请日：2002-09-10
申请人： Tao Pi , Patrick J. Crotty
发明人： Tao Pi , Patrick J. Crotty
IPC分类号： H03L19173
CPC分类号： H03K19/17764 , H03K17/693 , H03K19/1737 , H03K19/17728 , H03K19/1778
摘要： A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.
摘要翻译：用于现场可编程门阵列（FPGA）的查找表（LUT）被设计为在低电压电平下可靠地运行。低电压LUT使用CMOS传输门而不是未配对的N沟道晶体管来选择一个存储单元输出作为LUT输出信号。因此，通过栅极不会发生电压降。虽然该修改显着增加了LUT的总门控数量，但是通过去除当前设计中所需的半锁存器以及通过去除由该修改不必要的初始化电路可以减轻该缺点。一些实施例包括降低存储器单元和输出端子之间的通路数量的解码器，代价是在穿过解码器的输入路径上增加延迟。

10. 发明授权

US5898320A Programmable interconnect point having reduced crowbar current 失效
标题翻译：可编程互连点具有减少的撬棒电流
公开(公告)号：US5898320A
公开(公告)日：1999-04-27
申请号：US823270
申请日：1997-03-27
申请人： Richard C. Li , Hy V. Nguyen , Patrick J. Crotty
发明人： Richard C. Li , Hy V. Nguyen , Patrick J. Crotty
IPC分类号： H03K19/017
CPC分类号： H03K19/018585 , H03K19/00361
摘要： Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.
摘要翻译：通过在电源和地之间插入晶体管开关来解决由于缓冲的可编程互连点处的输入信号转换引起的与过量的短路电流相关的问题。插入的开关与输入缓冲器串联并由也控制互连的通过/不通过状态的存储器单元控制。断开插入开关在存储单元输出导致互连的无通状态时，阻断在切换期间流动的电流。

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