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1. 发明授权

US08743653B1 Reducing dynamic power consumption of a memory circuit 有权
标题翻译：降低存储电路的动态功耗
公开(公告)号：US08743653B1
公开(公告)日：2014-06-03
申请号：US13528620
申请日：2012-06-20
申请人： Sridhar Narayanan , Sridhar Subramanian , Subodh Kumar , Matthew H. Klein
发明人： Sridhar Narayanan , Sridhar Subramanian , Subodh Kumar , Matthew H. Klein
IPC分类号： G11C7/22 , G11C7/10 , G11C11/4076
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/222 , G11C11/4076
摘要： A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.
摘要翻译：电路可以包括耦合到存储器的地址总线的地址评估电路，并被配置为响应于确定地址总线上的地址对于从前一个时钟周期的当前时钟周期没有改变来产生第一控制信号。电路可以包括耦合到存储器并被配置为产生第二控制信号的写入使能评估电路，其响应于确定存储器的写使能信号对于当前时钟周期和先前的时钟周期被取消置位。电路可以包括耦合到存储器的时钟使能端口的时钟使能电路，并被配置为响应于第一控制信号和第二控制信号而将时钟使能信号产生到存储器的时钟使能端口。

2. 发明授权

US08104012B1 System and methods for reducing clock power in integrated circuits 有权
标题翻译：集成电路中降低时钟功率的系统和方法
公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译：在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。提供了一种用于在EDA工具上执行该方法的系统。可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

3. 发明授权

US08058905B1 Clock distribution to facilitate gated clocks 有权
标题翻译：时钟分配方便门控时钟
公开(公告)号：US08058905B1
公开(公告)日：2011-11-15
申请号：US12363722
申请日：2009-01-31
申请人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
发明人： Matthew H. Klein , Richard W. Swanson , Trevor J. Bauer , Steven P. Young , Andy DeBaets
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.
摘要翻译：描述了便于在诸如现场可编程门阵列（FPGA）的可编程集成电路中分配门控时钟的电路和方法。通过在分层时钟分配网络中的不同位置提供门控时钟驱动器电路，可以在FPGA中实现动态功耗。门控时钟电路通过使能信号为时钟元件提供门控时钟信号。包括时钟元件和可编程互连瓦片的可配置逻辑块（CLB）设置在门阵列中。时钟信号通过时钟分配网络分发给CLB。对应于一些时钟信号提供时钟使能信号。在时钟分配网络中提供时钟缓冲器或驱动器，将门控时钟信号驱动到CLB。通过在FPGA的部分不活动时使用本发明的一个或多个实施例来禁用某些时钟元件，动态功耗降低。

4. 发明授权

US08874999B1 Pulse width determination for phase detection 有权
标题翻译：脉冲宽度确定相位检测
公开(公告)号：US08874999B1
公开(公告)日：2014-10-28
申请号：US13362505
申请日：2012-01-31
申请人： David F. Taylor , Matthew H. Klein , Vincent Vendramini
发明人： David F. Taylor , Matthew H. Klein , Vincent Vendramini
IPC分类号： H03M13/00
CPC分类号： H03L7/1976 , H03L7/0994 , H03L2207/50
摘要： An embodiment of an apparatus includes a detector to receive a first input signal and a second input signal to provide a first error signal and a second error signal. A pulse width determination block receives the first and second error signals, as well as a digital oscillating signal, to output a first pulse width value and a second pulse width value, respectively. A pulse width accumulator accumulates the first and second pulse width values responsive to at least one cycle of the digital oscillating signal to provide a first accumulated value and a second accumulated value. An error generator provides an error value as a difference between the first accumulated value and the second accumulated value. The error value represents a pulse width difference between the first input signal and the second input signal indicative of a phase difference between the first input signal and the second input signal.
摘要翻译：装置的实施例包括用于接收第一输入信号和第二输入信号以提供第一误差信号和第二误差信号的检测器。脉冲宽度确定块接收第一和第二误差信号以及数字振荡信号，以分别输出第一脉冲宽度值和第二脉冲宽度值。脉冲宽度累加器响应于数字振荡信号的至少一个周期积累第一和第二脉冲宽度值，以提供第一累积值和第二累积值。误差发生器提供误差值作为第一累积值和第二累积值之间的差。误差值表示第一输入信号和第二输入信号之间的脉冲宽度差，表示第一输入信号和第二输入信号之间的相位差。

5. 发明授权

US08665928B1 Circuit for generating an output clock signal synchronized to an input clock signal 有权
标题翻译：用于产生与输入时钟信号同步的输出时钟信号的电路
公开(公告)号：US08665928B1
公开(公告)日：2014-03-04
申请号：US13030558
申请日：2011-02-18
申请人： Matthew H. Klein , David F. Taylor
发明人： Matthew H. Klein , David F. Taylor
IPC分类号： H04B3/36 , H04L25/20 , H04L25/52 , H03D3/24
CPC分类号： H04L25/247 , H04L25/4908
摘要： A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.
摘要翻译：电路产生与输入时钟信号同步的输出时钟信号。该电路包括参考时钟端口，相位内插器和相位控制器。参考时钟端口接收参考时钟信号。相位插值器产生作为可变控制值的函数的两个参考相位之间的内插的输出时钟信号。参考相位由参考时钟信号产生并具有参考频率。相位控制器产生提供相位旋转速率的变量控制值。输出时钟信号的输出频率等于参考频率和相位旋转速率之和。输出频率与输入时钟信号的输入频率相匹配。

6. 发明申请

US20110276321A1 DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE 有权
标题翻译：器件特定的工作电压配置
公开(公告)号：US20110276321A1
公开(公告)日：2011-11-10
申请号：US12774110
申请日：2010-05-05
申请人： Tim Tuan , Daniel Chung , Ronald Cline , Andy DeBaets , Matthew H. Klein
发明人： Tim Tuan , Daniel Chung , Ronald Cline , Andy DeBaets , Matthew H. Klein
IPC分类号： G06F17/50 , G05F1/10
CPC分类号： G06F17/5054 , G06F17/5068 , G06F2217/84
摘要： A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.
摘要翻译：提供了用于器件特定配置工作电压的方法和电路。分析电路设计以确定电路设计的最大门级延迟。确定对应于最大门级延迟的最小电压值以及对应于默认门级延迟的默认电压值。确定对应于最小电压和默认电压值的电压缩放因子。合成电路设计，使得合成设计包括电压缩放值。合成设计指定将工作电压设置为由电压缩放值缩放的启动电压值的值。

7. 发明授权

US09015023B2 Device specific configuration of operating voltage 有权
标题翻译：器件具体配置工作电压
公开(公告)号：US09015023B2
公开(公告)日：2015-04-21
申请号：US12774110
申请日：2010-05-05
申请人： Tim Tuan , Daniel Chung , Ronald Cline , Andy DeBaets , Matthew H. Klein
发明人： Tim Tuan , Daniel Chung , Ronald Cline , Andy DeBaets , Matthew H. Klein
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5068 , G06F2217/84
摘要： A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.
摘要翻译：提供了用于器件特定配置工作电压的方法和电路。分析电路设计以确定电路设计的最大门级延迟。确定对应于最大门级延迟的最小电压值以及对应于默认门级延迟的默认电压值。确定对应于最小电压和默认电压值的电压缩放因子。合成电路设计，使得合成设计包括电压缩放值。合成设计指定将工作电压设置为由电压缩放值缩放的启动电压值的值。

8. 发明授权

US08030967B1 Method and apparatus involving a receiver with a selectable performance characteristic 有权
标题翻译：涉及具有可选性能特征的接收机的方法和装置
公开(公告)号：US08030967B1
公开(公告)日：2011-10-04
申请号：US12363653
申请日：2009-01-30
申请人： Jian Tan , Matthew H. Klein , Atul V. Ghia
发明人： Jian Tan , Matthew H. Klein , Atul V. Ghia
IPC分类号： H03K19/094 , H03K3/00 , H03B1/00
CPC分类号： H03K19/17788 , H03K19/017581
摘要： A circuit has a programmable mode control section, and a receiver section with first and second input terminals and an output terminal. The method and apparatus involve setting the mode control section to one of first and second states in response to user input, and operating the receiver section in first and second operational mode when the mode control section respectively has the first and second states, wherein in the first operational mode the receiver section provides higher performance and consumes more power than in the second operational mode.
摘要翻译：电路具有可编程模式控制部分，以及具有第一和第二输入端子和输出端子的接收器部分。所述方法和装置包括响应于用户输入将模式控制部分设置为第一和第二状态之一，并且当模式控制部分别具有第一和第二状态时，以第一和第二操作模式操作接收器部分，其中在第一操作模式，接收器部分提供比第二操作模式更高的性能并且消耗更多的功率。

9. 发明授权

US08018250B1 Input/output block and operation thereof 有权
标题翻译：输入/输出块及其操作
公开(公告)号：US08018250B1
公开(公告)日：2011-09-13
申请号：US12907850
申请日：2010-10-19
申请人： Matthew H. Klein , Jian Tan , Ketan Sodha , Madan M. Patra
发明人： Matthew H. Klein , Jian Tan , Ketan Sodha , Madan M. Patra
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/177
摘要： An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to the removing of the first tri-state condition, the input driver is placed in a second tri-state condition.
摘要翻译：公开了一种用于操作输入/输出块的方法的实施例。对于该方法的该实施例，为输入驱动器的第一禁用信号设置第一属性。从输出驱动程序中删除第一个三态条件。响应于去除第一三态条件，输入驱动器被置于第二三态条件中。

10. 发明授权

US07589557B1 Reversible input/output delay line for bidirectional input/output blocks 有权
标题翻译：用于双向输入/输出块的可逆输入/输出延迟线
公开(公告)号：US07589557B1
公开(公告)日：2009-09-15
申请号：US11405901
申请日：2006-04-18
申请人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
发明人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
IPC分类号： H03K19/173
CPC分类号： H03K5/159 , H03K19/017581 , H03K19/01759
摘要： An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.
摘要翻译：输入/输出（I / O）结构包括在用户设计中可用于输入路径，输出路径或输入和输出路径的延迟元件。在第一模式中，延迟元件包括在输入路径中。在第二模式中，延迟元件包括在输出路径中。在第三模式中，I / O结构包括输出信号路径和输入信号路径中的延迟，例如通过利用输出三态信号来控制延迟线的方向。当输出缓冲区正在驱动时，延迟被插入到输出路径中。当输出缓冲器被三态时，延迟被插入到输入路径中。因此，单个延迟元件由使用相同I / O焊盘的输入和输出信号动态共享。在可选的第四模式中，延迟元件被输入和输出信号旁路。

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