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1. 发明授权

US08099564B1 Programmable memory controller 有权
标题翻译：可编程存储控制器
公开(公告)号：US08099564B1
公开(公告)日：2012-01-17
申请号：US11891378
申请日：2007-08-10
申请人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
发明人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.
摘要翻译：在可编程集成电路中实现的存储器控制器可以包括具有命令寄存器和多个数据先进先出（FIFO）存储器的用户接口，其中命令寄存器可以接收数据FIFO存储器的地址多个数据FIFO存储器。耦合到用户界面的核心控制器可以响应于来自用户界面的指令来生成控制信号，该控制信号在耦合到核心控制器的存储器设备内启动操作。与核心控制器，用户界面和存储设备耦合的物理层可以响应于存储器设备的读取操作，根据在命令中接收的地址存储从所选择的数据FIFO存储器中的存储器设备接收的数据寄存器。

2. 发明授权

US07759968B1 Method of and system for verifying configuration data 有权
标题翻译：验证配置数据的方法和系统
公开(公告)号：US07759968B1
公开(公告)日：2010-07-20
申请号：US11527882
申请日：2006-09-27
申请人： Jameel Hussein , Dean C. Moss , James A. Walstrum, Jr.
发明人： Jameel Hussein , Dean C. Moss , James A. Walstrum, Jr.
IPC分类号： H03K19/173
CPC分类号： H03K19/17764
摘要： A method of verifying configuration data to be loaded into a device having programmable logic is described. The method comprising the steps of validating a configuration bitstream to be loaded into the device having programmable logic; storing a validation indicator with the configuration bitstream in a non-volatile memory device; and configuring the programmable logic according to the configuration bitstream if the validation indicator indicates that valid data is stored in the non-volatile memory device. A system for verifying configuration data to be loaded into a device having programmable logic is also described.
摘要翻译：描述了将要加载到具有可编程逻辑的设备中的配置数据的验证方法。该方法包括以下步骤：验证要加载到具有可编程逻辑的设备中的配置比特流; 将配置比特流的验证指示符存储在非易失性存储器设备中; 以及如果所述验证指示符指示有效数据存储在所述非易失性存储器设备中，则根据所述配置比特流来配置所述可编程逻辑。还描述了用于验证要加载到具有可编程逻辑的设备的配置数据的系统。

3. 发明授权

US07626423B1 Slew rate control for output signals 有权
标题翻译：输出信号的转换速率控制
公开(公告)号：US07626423B1
公开(公告)日：2009-12-01
申请号：US11999196
申请日：2007-12-03
申请人： Richard C. Li , Phillip A. Young , James A. Walstrum, Jr.
发明人： Richard C. Li , Phillip A. Young , James A. Walstrum, Jr.
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585
摘要： An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.
摘要翻译：输出电路允许选择性地调节其输出信号的转换速率。输出驱动电路包括一个输出驱动器和预驱动电路。输出驱动器包括耦合在第一电源电压和输出端之间的输出晶体管。预驱动器电路响应于模式控制信号选择性地调节输出晶体管的栅极和第二电源电压之间的串联电阻。

4. 发明授权

US07550324B1 Interface port for electrically programmed fuses in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中电气编程保险丝的接口端口
公开(公告)号：US07550324B1
公开(公告)日：2009-06-23
申请号：US11985501
申请日：2007-11-15
申请人： James A. Walstrum, Jr. , Steven E. McNeil , Shalin Umesh Sheth
发明人： James A. Walstrum, Jr. , Steven E. McNeil , Shalin Umesh Sheth
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00 , G06F17/50
CPC分类号： H03K19/17768
摘要： A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.
摘要翻译：可编程逻辑器件（PLD）包括可编程的PLD标识符的电可编程熔丝。 PLD还包括可编程瓦片和耦合到移位寄存器和可编程瓦片子集的接口端口。接口端口包括控制端口和第一和第二串行数据信号。移位寄存器具有并行输入端口，用于响应于控制端口的读取命令从该组电可编程保险丝加载标识符。移位寄存器响应于控制端口的移位指令而逐行移位一位，包括通过第一串行数据信号将可编程块的子集移位到移位寄存器，并将位从移位寄存器移位到可编程瓦片的子集经由第二串行数据信号。

5. 发明授权

US08863230B1 Methods of authenticating a programmable integrated circuit in combination with a non-volatile memory device 有权
标题翻译：将可编程集成电路与非易失性存储器件组合认证的方法
公开(公告)号：US08863230B1
公开(公告)日：2014-10-14
申请号：US11450755
申请日：2006-06-09
申请人： Steven K. Knapp , James A. Walstrum, Jr. , Shalin Umesh Sheth
发明人： Steven K. Knapp , James A. Walstrum, Jr. , Shalin Umesh Sheth
IPC分类号： G06F21/00
CPC分类号： G06F21/73 , G06F21/44 , G06F21/71
摘要： Methods of authenticating a combination of a programmable IC and a non-volatile memory device, where the non-volatile memory device stores a configuration data stream implementing a user design in the programmable IC. A first identifier unique to the programmable IC is stored in non-volatile memory in the programmable IC. A second identifier unique to the non-volatile memory device is stored in the non-volatile memory device. As part of the process in which the configuration data stream is used to program the programmable IC with the user design, a function is performed on the two identifiers, producing a key specific to the programmable IC/non-volatile memory device combination. The key is then compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled.
摘要翻译：认证可编程IC和非易失性存储器件的组合的方法，其中非易失性存储器件存储在可编程IC中实现用户设计的配置数据流。可编程IC特有的第一标识符被存储在可编程IC中的非易失性存储器中。非易失性存储器件唯一的第二标识符被存储在非易失性存储器件中。作为使用配置数据流以用户设计对可编程IC进行编程的过程的一部分，对两个标识符执行功能，产生专用于可编程IC /非易失性存储器件组合的密钥。然后将关键字与预期值进行比较。当密钥与期望值匹配时，用户设计被启用。当该键与期望值不匹配时，用户设计的至少一部分被禁用。

6. 发明授权

US07987358B1 Methods of authenticating a user design in a programmable integrated circuit 有权
标题翻译：在可编程集成电路中认证用户设计的方法
公开(公告)号：US07987358B1
公开(公告)日：2011-07-26
申请号：US11450756
申请日：2006-06-09
申请人： James A. Walstrum, Jr. , Steven K. Knapp , Shalin Umesh Sheth
发明人： James A. Walstrum, Jr. , Steven K. Knapp , Shalin Umesh Sheth
IPC分类号： H04L29/06
CPC分类号： G06F21/123
摘要： Methods of authenticating a user design in a programmable integrated circuit. The methods utilize an identifier unique to the programmable IC and a data word taken from the user design. The data word can be unique to the design and can include a string of data taken from the configuration data for the design, or the values of circuit nodes read from selected points throughout the design. A function is performed on the identifier and the data word, producing a key specific to the user design as implemented in that programmable IC. The key is compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled. Circuitry for performing the steps of the method can be implemented in the programmable resources of the programmable IC.
摘要翻译：在可编程集成电路中认证用户设计的方法。该方法利用可编程IC特有的标识符和从用户设计中获取的数据字。数据字可以是设计唯一的，并且可以包括从设计的配置数据中获取的一串数据，或者在整个设计中从选定点读取的电路节点的值。对标识符和数据字执行功能，产生专用于该可编程IC中实现的用户设计的密钥。将关键字与预期值进行比较。当密钥与期望值匹配时，用户设计被启用。当该键与期望值不匹配时，用户设计的至少一部分被禁用。用于执行该方法的步骤的电路可以在可编程IC的可编程资源中实现。

7. 发明授权

US07853811B1 Suspend mode operation for reduced power 有权
标题翻译：挂起模式操作降低功耗
公开(公告)号：US07853811B1
公开(公告)日：2010-12-14
申请号：US11498467
申请日：2006-08-03
申请人： James A. Walstrum, Jr. , Mark A. Moran , Jinsong Oliver Huang , Patrick J. Crotty
发明人： James A. Walstrum, Jr. , Mark A. Moran , Jinsong Oliver Huang , Patrick J. Crotty
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.
摘要翻译：集成电路（300）包括一个挂起电路，该暂停电路包括用于接收暂停信号的第一输入端，产生唤醒信号的第一输出端，并输出以向各种集成电路资源提供控制信号。在暂停模式期间，暂停电路通过将其输出引脚驱动到由相应的模式选择信号选择的多个预定状态中的一个并通过将其同步元件锁定到已知状态来暂停集成电路资源的操作。在暂停模式终止时，电路根据用户定义的定时调度重新激活集成电路资源。用户定义的定时计划和模式选择信号可以在其配置期间被提供给集成电路，作为配置比特流的一部分。

8. 发明授权

US07671624B1 Method to reduce configuration solution using masked-ROM 有权
标题翻译：使用掩蔽ROM来减少配置方案的方法
公开(公告)号：US07671624B1
公开(公告)日：2010-03-02
申请号：US11546057
申请日：2006-10-10
申请人： James A. Walstrum, Jr.
发明人： James A. Walstrum, Jr.
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177
摘要： A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.
摘要翻译：封装的PLD解决方案包括具有掩蔽的只读存储器（ROM）的第一管芯，其在其制造期间被编程以存储配置数据，并且包括具有PLD的第二管芯，PLD包括多个可配置资源，共同配置为实现电路设计由配置数据体现。第一管芯与第二管芯电连接，并且第一管芯和第二管芯都被堆叠并封装在一起以形成封装的PLD溶液。掩模ROM和PLD的制造商将配置数据编程到掩蔽ROM中。

9. 发明授权

US07339400B1 Interface port for electrically programmed fuses in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中电气编程保险丝的接口端口
公开(公告)号：US07339400B1
公开(公告)日：2008-03-04
申请号：US11449935
申请日：2006-06-09
申请人： James A. Walstrum, Jr. , Steven E. McNeil , Shalin Umesh Sheth
发明人： James A. Walstrum, Jr. , Steven E. McNeil , Shalin Umesh Sheth
IPC分类号： H03K19/173 , H03K19/177 , H03K19/00
CPC分类号： H03K19/17768
摘要： A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.
摘要翻译：可编程逻辑器件（PLD）包括可编程的PLD标识符的电可编程熔丝。 PLD还包括可编程瓦片和耦合到移位寄存器和可编程瓦片子集的接口端口。接口端口包括控制端口和第一和第二串行数据信号。移位寄存器具有并行输入端口，用于响应于控制端口的读取命令从该组电可编程保险丝加载标识符。移位寄存器响应于控制端口的移位指令而逐行移位一位，包括通过第一串行数据信号将可编程块的子集移位到移位寄存器，并将位从移位寄存器移位到可编程瓦片的子集经由第二串行数据信号。

10. 发明授权

US07669102B1 JTAG to SPI PROM conduit 有权
标题翻译： JTAG到SPI PROM管道
公开(公告)号：US07669102B1
公开(公告)日：2010-02-23
申请号：US11514425
申请日：2006-09-01
申请人： Wayne E. Wennekamp , Randal Kuramoto , James A. Walstrum, Jr. , Sanja Srivastava , Neil G. Jacobson
发明人： Wayne E. Wennekamp , Randal Kuramoto , James A. Walstrum, Jr. , Sanja Srivastava , Neil G. Jacobson
IPC分类号： G01R31/28 , G06F7/38 , H03K19/173 , G06F13/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/0401 , G11C2029/5602 , H03K19/1776
摘要： A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.
摘要翻译：通过PLD的JTAG端口配置与可编程逻辑器件（PLD）耦合的存储器。加载到PLD的软核连接到JTAG端口和存储器。一个外部编程主机设备连接到JTAG端口，通过JTAG端口和软核向内存发送指令和数据并从存储器接收数据。加载同步JTAG指令，并使用JTAG端口状态机的移位数据状态。编程主机设备和软核同步，存储芯片选择被断言。诸如READ，WRITE或ERASE之类的存储器指令被加载到存储器中。状态机的RTI状态用于等待指令完成，芯片选择被置为无效。从使用Shift Data状态开始处理另一条指令。或者，PLD移位数据寄存器与软核一起使用。

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