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1. 发明申请

WO2010070676A3 INTUITIVE ELECTRONIC CIRCUIT 审中-公开
标题翻译：直观电子电路
公开(公告)号：WO2010070676A3
公开(公告)日：2010-08-19
申请号：PCT/IN2009000700
申请日：2009-12-03
申请人： TYCKA DESIGN PRIVATE LTD , MOHAMMED SUHURA SHANAVAS , SRIDHAR SUBRAMANIAN , NARKAR SUNAY , BATHE DATTATRAYA CHANDRAKANT , PANCHANATHAN SENTHIL KUMAR , SUBRAMANIAM KUBERASAMPATH
发明人： MOHAMMED SUHURA SHANAVAS , SRIDHAR SUBRAMANIAN , NARKAR SUNAY , BATHE DATTATRAYA CHANDRAKANT , PANCHANATHAN SENTHIL KUMAR , SUBRAMANIAM KUBERASAMPATH
IPC分类号： H02J9/00 , H02J7/00
CPC分类号： H02J9/065 , H05B35/00 , H05B37/0209 , Y10T307/625
摘要： An apparatus according to various embodiments may detect the state of an external switch (14). An apparatus (1000) according to various embodiments may activate or deactivate an appliance based on the state of the external switch (14). An apparatus according to various embodiments may activate or deactivate an appliance based on the state of the external switch (14), even in the absence of grid power (3).
摘要翻译：根据各种实施例的装置可以检测外部开关（14）的状态。根据各种实施例的设备（1000）可以基于外部开关（14）的状态激活或停用设备。根据各种实施例的设备可以即使在没有电力（3）的情况下也可以基于外部开关（14）的状态激活或停用设备。

2. 发明申请

WO2010070676A2 INTUITIVE ELECTRONIC CIRCUIT 审中-公开
标题翻译：直观电子电路
公开(公告)号：WO2010070676A2
公开(公告)日：2010-06-24
申请号：PCT/IN2009/000700
申请日：2009-12-03
申请人： TYCKA DESIGN PRIVATE LIMITED , MOHAMMED SUHURA, Shanavas , SRIDHAR, Subramanian , NARKAR, Sunay , BATHE, Dattatraya Chandrakant , PANCHANATHAN, Senthil Kumar , SUBRAMANIAM, Kuberasampath
发明人： MOHAMMED SUHURA, Shanavas , SRIDHAR, Subramanian , NARKAR, Sunay , BATHE, Dattatraya Chandrakant , PANCHANATHAN, Senthil Kumar , SUBRAMANIAM, Kuberasampath
CPC分类号： H02J9/065 , H05B35/00 , H05B37/0209 , Y10T307/625
摘要： An apparatus according to various embodiments may detect the state of an external switch. An apparatus according to various embodiments may activate or deactivate an appliance based on the state of the external switch. An apparatus according to various embodiments may activate or deactivate an appliance based on the state of the external switch, even in the absence of grid power.
摘要翻译：根据各种实施例的装置可以检测外部开关的状态。根据各种实施例的装置可以基于外部开关的状态来激活或去激活设备。根据各种实施例的设备可以基于外部开关的状态来激活或去激活设备，即使在没有电力的情况下也是如此。

3. 发明授权

US08743653B1 Reducing dynamic power consumption of a memory circuit 有权
标题翻译：降低存储电路的动态功耗
公开(公告)号：US08743653B1
公开(公告)日：2014-06-03
申请号：US13528620
申请日：2012-06-20
申请人： Sridhar Narayanan , Sridhar Subramanian , Subodh Kumar , Matthew H. Klein
发明人： Sridhar Narayanan , Sridhar Subramanian , Subodh Kumar , Matthew H. Klein
IPC分类号： G11C7/22 , G11C7/10 , G11C11/4076
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/222 , G11C11/4076
摘要： A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.
摘要翻译：电路可以包括耦合到存储器的地址总线的地址评估电路，并被配置为响应于确定地址总线上的地址对于从前一个时钟周期的当前时钟周期没有改变来产生第一控制信号。电路可以包括耦合到存储器并被配置为产生第二控制信号的写入使能评估电路，其响应于确定存储器的写使能信号对于当前时钟周期和先前的时钟周期被取消置位。电路可以包括耦合到存储器的时钟使能端口的时钟使能电路，并被配置为响应于第一控制信号和第二控制信号而将时钟使能信号产生到存储器的时钟使能端口。

4. 发明申请

US20050083945A1 Method and apparatus for providing internal table extensibility based on product configuration 失效
标题翻译：基于产品配置提供内部表可扩展性的方法和装置
公开(公告)号：US20050083945A1
公开(公告)日：2005-04-21
申请号：US10687789
申请日：2003-10-17
申请人： Gaurav Singh , Ali Kani , Kiran Kattel , Sridhar Subramanian , Brian Yang
发明人： Gaurav Singh , Ali Kani , Kiran Kattel , Sridhar Subramanian , Brian Yang
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L41/0816
摘要： A configurable lookup table system including a first controller coupled to a first lookup table and a second controller coupled to a second lookup table is disclosed. The first controller configures the first lookup table for a first type lookup, which can be a Layer 2 or Media Access Control (MAC) type. The second controller configures the second lookup table based on a mode determination. If in a first mode, the second lookup table can be configured for a second type lookup, which can be a Layer 3 or Internet Protocol (IP) type. If in a second mode, the second lookup table can be configured for the first type lookup. This approach provides an efficient scheme for controlling and using multiple internal lookup tables for a variety of product configurations.
摘要翻译：公开了一种可配置的查找表系统，其包括耦合到第一查找表的第一控制器和耦合到第二查找表的第二控制器。第一个控制器为第一个类型查找配置第一个查找表，它可以是第二层或介质访问控制（MAC）类型。第二控制器基于模式确定来配置第二查找表。如果在第一模式中，可以将第二查找表配置为第二类型查找，其可以是第3层或互联网协议（IP）类型。如果在第二模式中，可以为第一类型查找配置第二查找表。这种方法提供了一种用于控制和使用多种内部查找表用于各种产品配置的有效方案。

5. 发明授权

US08219946B1 Method for clock gating circuits 有权
标题翻译：时钟门控电路的方法
公开(公告)号：US08219946B1
公开(公告)日：2012-07-10
申请号：US12835638
申请日：2010-07-13
申请人： Chaiyasit Manovit , Wanlin Cao , Sridhar Narayanan , Sridhar Subramanian
发明人： Chaiyasit Manovit , Wanlin Cao , Sridhar Narayanan , Sridhar Subramanian
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： In one embodiment, a method is provided for generating clock gating circuitry for a circuit design model. A Boolean expression of path sensitization is determined for each gate element in the netlist of a circuit design. For each gate element, a conjunction of the Boolean expression of the path sensitization and a Boolean expression of a disjunction of the observability conditions of one or more subsequent gates is determined to produce an intermediate Boolean expression. Intermediate Boolean expressions are backward retimed to produce the respective Boolean expression of the observability conditions of the each gate element. Clock gating circuits that implement the respective Boolean expression of the observability conditions of one or more of the plurality of interconnected gate elements are generated and incorporated into the circuit design model.
摘要翻译：在一个实施例中，提供了一种用于产生用于电路设计模型的时钟选通电路的方法。确定电路设计网表中每个门元件的路径敏感度的布尔表达式。对于每个门元件，确定路径敏化的布尔表达式与一个或多个后续门的可观察性条件的分离的布尔表达式的结合以产生中间布尔表达式。中间布尔表达式被反向重新定时以产生每个门元件的可观察性条件的各自的布尔表达式。实现实现多个互连门元件中的一个或多个的可观察性条件的相应布尔表达式的时钟选通电路被生成并并入电路设计模型中。

6. 发明授权

US07471682B2 Method and apparatus for providing internal table extensibility based on product configuration 失效
标题翻译：基于产品配置提供内部表可扩展性的方法和装置
公开(公告)号：US07471682B2
公开(公告)日：2008-12-30
申请号：US10687789
申请日：2003-10-17
申请人： Gaurav Singh , Ali Kani , Kiran Kattel , Sridhar Subramanian , Brian Hang Wai Yang
发明人： Gaurav Singh , Ali Kani , Kiran Kattel , Sridhar Subramanian , Brian Hang Wai Yang
IPC分类号： H04L12/56
CPC分类号： H04L41/0816
摘要： A configurable lookup table system including a first controller coupled to a first lookup table and a second controller coupled to a second lookup table is disclosed. The first controller configures the first lookup table for a first type lookup, which can be a Layer 2 or Media Access Control (MAC) type. The second controller configures the second lookup table based on a mode determination. If in a first mode, the second lookup table can be configured for a second type lookup, which can be a Layer 3 or Internet Protocol (IP) type. If in a second mode, the second lookup table can be configured for the first type lookup. This approach provides an efficient scheme for controlling and using multiple internal lookup tables for a variety of product configurations.
摘要翻译：公开了一种可配置的查找表系统，其包括耦合到第一查找表的第一控制器和耦合到第二查找表的第二控制器。第一个控制器为第一个类型查找配置第一个查找表，它可以是第二层或介质访问控制（MAC）类型。第二控制器基于模式确定来配置第二查找表。如果在第一模式中，可以将第二查找表配置为第二类型查找，其可以是第3层或互联网协议（IP）类型。如果在第二模式中，可以为第一类型查找配置第二查找表。这种方法提供了一种用于控制和使用多种内部查找表用于各种产品配置的有效方案。

7. 发明申请

US20070271402A1 Partially Populated, Hierarchical Crossbar 有权
标题翻译：部分填充，分层交叉
公开(公告)号：US20070271402A1
公开(公告)日：2007-11-22
申请号：US11832841
申请日：2007-08-02
申请人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
发明人： Sridhar Subramanian , James Keller , George Yiu , Ruchi Wadhawan
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，装置包括多个代理和互连。在一个实施方案中，多种试剂包括第一至第四试剂。互连包括可切换的多个段（例如，使用多个选择电路）以形成代理之间的通信路径，并且第一段包括在从第一代理到第二代理的第一通信路径中，并且还包括在从第三代理到第四代理的第二通信路径中。在另一实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。在另一个实施例中，仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

8. 发明申请

US20050083927A1 Method and apparatus for packet transmit queue 失效
标题翻译：分组传输队列的方法和装置
公开(公告)号：US20050083927A1
公开(公告)日：2005-04-21
申请号：US10687786
申请日：2003-10-17
申请人： Wei-han Lien , Brian Yang , Sridhar Subramanian
发明人： Wei-han Lien , Brian Yang , Sridhar Subramanian
IPC分类号： H04L12/56
CPC分类号： H04L47/2441 , H04L45/00 , H04L45/16 , H04L45/60 , H04L47/15 , H04L49/90 , H04L49/901
摘要： A packet transmit queue control system including a first data structure, a second data structure, a packet controller, and a port transmit controller is disclosed. The first data structure can include a plurality of linked-list data structures and can store unicast type packet pointers. The second data structure can include a plurality of first-in first-out (FIFO) structures and can store multicast type packet pointers. The packet controller can receive a first sequence of unicast and/or multicast type packets. The port transmit controller can provide a second sequence of the unicast and/or multicast type packets. Further, each of the plurality of FIFO structures can correspond to an output port of the system.
摘要翻译：公开了包括第一数据结构，第二数据结构，分组控制器和端口发送控制器的分组发送队列控制系统。第一数据结构可以包括多个链表列表数据结构，并且可以存储单播类型分组指针。第二数据结构可以包括多个先进先出（FIFO）结构，并且可以存储多播类型分组指针。分组控制器可以接收单播和/或多播类型分组的第一序列。端口发送控制器可以提供单播和/或多播类型分组的第二序列。此外，多个FIFO结构中的每一个可以对应于系统的输出端口。

9. 发明授权

US07746116B1 Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis 有权
标题翻译：通过使用前馈静态输入分析对数字集成电路进行时钟门控的方法和装置
公开(公告)号：US07746116B1
公开(公告)日：2010-06-29
申请号：US12356797
申请日：2009-01-21
申请人： Sridhar Narayanan , Chaiyasit Manovit , Sridhar Subramanian , Gerald Gras
发明人： Sridhar Narayanan , Chaiyasit Manovit , Sridhar Subramanian , Gerald Gras
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： One aspect of the invention relates to a device including a first storage element and a first clock gating element, wherein a data input of the first storage element is coupled to an output of a combinatorial logic (CL) element, wherein the first storage element is clock-gated with the first clock gating element using a first clock enable signal to generate a clock signal for the first storage element, wherein the first clock enable signal is generated to suppress the clock signal in the first clock gating element when each of the at least one data input of the CL element is in a second quiescence inducing condition with respect to the clock signal at the same time as when each of the at least one control input of the CL element is in the first quiescence inducing condition.
摘要翻译：本发明的一个方面涉及一种包括第一存储元件和第一时钟门控元件的器件，其中第一存储元件的数据输入耦合到组合逻辑（CL）元件的输出，其中第一存储元件是利用第一时钟门控元件对第一时钟门控元件进行时钟门控，以使用第一时钟使能信号来产生用于第一存储元件的时钟信号，其中产生第一时钟使能信号以在第一时钟门控元件中的每个时钟门控元件当CL元件的至少一个控制输入中的每一个处于第一静止诱导条件时，相对于时钟信号，CL元件的至少一个数据输入处于第二静态诱导条件。

10. 发明申请

US20070050564A1 Combined buffer for snoop, store merging, load miss, and writeback operations 有权
标题翻译：组合缓冲区，用于侦听，存储合并，加载错误和回写操作
公开(公告)号：US20070050564A1
公开(公告)日：2007-03-01
申请号：US11215604
申请日：2005-08-30
申请人： Ramesh Gunna , Po-Yung Chang , Sridhar Subramanian , James Keller , Tse-Yuh Yeh
发明人： Ramesh Gunna , Po-Yung Chang , Sridhar Subramanian , James Keller , Tse-Yuh Yeh
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.
摘要翻译：在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接收的窥探请求的地址。所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中第一个队列。响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址第二个队列中的缓冲区条目。

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