专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07944261B1 Method and apparatus for detecting clock loss 有权
标题翻译：检测时钟损耗的方法和装置
公开(公告)号：US07944261B1
公开(公告)日：2011-05-17
申请号：US11999194
申请日：2007-12-03
申请人： Patrick T. Lynch , Amit Wadhwa
发明人： Patrick T. Lynch , Amit Wadhwa
IPC分类号： H03L7/06
CPC分类号： H03L7/08
摘要： Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.
摘要翻译：用于检测时钟电路中的时钟损耗的方法和装置。本发明的一个实例涉及检测输入到数字时钟管理器的反馈时钟信号的损耗，其中反馈时钟信号是从参考时钟信号导出的。提供时钟分频器以产生来自反馈时钟信号的分频反馈时钟信号。第一对触发器被配置为在参考时钟信号的连续边缘上存储划分的反馈时钟信号的采样。第二对触发器被配置为在参考时钟信号的反相的连续边缘上存储划分的反馈时钟信号的采样。检测逻辑被配置为检测第一对触发器和第二对触发器中的每一个是否存储相同的值。

2. 发明授权

US06788119B1 Delay line circuit providing clock pulse width restoration in delay lock loops 有权
标题翻译：延迟线电路在延迟锁定环路中提供时钟脉冲宽度恢复
公开(公告)号：US06788119B1
公开(公告)日：2004-09-07
申请号：US10402058
申请日：2003-03-27
申请人： Paul G. Hyland , Patrick T. Lynch
发明人： Paul G. Hyland , Patrick T. Lynch
IPC分类号： H03L706
CPC分类号： H03K5/1565 , H03K5/133 , H03K2005/00156 , H03L7/0814 , H03L7/087
摘要： Delay lock loops (DLLs) that include delay line circuits with an optional clock pulse width restoration feature, and programmable delay circuits that enable the DLLs. A DLL can include optional inversions before and after at least one of the delay lines included in the DLL. Because two inversions are provided, the overall logic of the delay line is preserved. A DLL typically includes several different delay lines. Therefore, by selectively inverting the clock signal between the delay lines, the effect of each delay line on the clock pulse width can be balanced to provide an output clock signal having a pulse width closer to that of the input clock than would be achievable without the use of such selective inversion. In embodiments where the DLL forms a portion of a programmable logic device (PLD), the optional inversions can be controlled, for example, by configuration memory cells of the PLD.
摘要翻译：延迟锁定循环（DLL），包括具有可选时钟脉冲宽度恢复功能的延迟线电路，以及启用DLL的可编程延迟电路。 DLL可以包括在DLL中包括的至少一个延迟线之前和之后的可选的反转。因为提供了两个反转，所以延迟线的整体逻辑被保留。 DLL通常包括几个不同的延迟线。因此，通过选择性地反转延迟线之间的时钟信号，可以平衡每个延迟线对时钟脉冲宽度的影响，以提供具有比可以实现的脉冲宽度更接近于输入时钟的脉冲宽度的输出时钟信号，而不需要使用这种选择性反转。在DLL形成可编程逻辑器件（PLD）的一部分的实施例中，可以例如通过PLD的配置存储器单元来控制可选的反转。

3. 发明授权

US06847246B1 Method and apparatus for reducing jitter and power dissipation in a delay line 有权
标题翻译：用于减少延迟线中的抖动和功耗的方法和装置
公开(公告)号：US06847246B1
公开(公告)日：2005-01-25
申请号：US10284725
申请日：2002-10-31
申请人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
发明人： Alireza S. Kaviani , Patrick T. Lynch , Paul G. Hyland , Patrick J. Crotty , Tao Pi
IPC分类号： H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.
摘要翻译：描述了用于降低延迟线中的功耗和抖动的方法和装置。延迟线包括多个延迟元件。多个延迟元件中的至少一个包括被配置为接收用于激活或去激活一个或多个延迟元件的栅极控制信号的栅极端子。延迟线还包括用于向多个延迟元件中的至少一个延迟元件的栅极端子提供栅极控制信号的栅极控制电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式