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    • 9. 发明授权
    • Array protection devices and fabrication method
    • 阵列保护装置及制造方法
    • US5523253A
    • 1996-06-04
    • US389529
    • 1995-02-16
    • Richard A. GilmourThomas J. HartswickDavid C. ThomasRonald R. UttechtErick G. Walton
    • Richard A. GilmourThomas J. HartswickDavid C. ThomasRonald R. UttechtErick G. Walton
    • H01L23/62H01L21/82
    • H01L23/62H01L2924/0002
    • The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.
    • 本公开提出了一种改进的集成电路,其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中,阻挡层是非易碎的,高熔点结构掩埋在钝化层中,覆盖包含保险丝的布线层,并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法,包括以下步骤:在其中具有有源区的半导体器件的表面上沉积绝缘层,在所述层中形成多个保险丝和电路元件,将所述保险丝和元件涂覆 第二绝缘层,图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽,以及在所述槽中沉积高熔点和非易碎材料。