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1. 发明申请

US20080206965A1 STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY 审中-公开
标题翻译：通过从Si（1-x-y）GexCy合金中制备碳制成的应变硅
公开(公告)号：US20080206965A1
公开(公告)日：2008-08-28
申请号：US11679308
申请日：2007-02-27
申请人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20
CPC分类号： H01L29/4983 , H01L21/02529 , H01L21/02532 , H01L21/02667 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.
摘要翻译：本发明公开了一种制备应变硅的方法，包括退火邻近硅区的碳掺杂硅 - 锗（SiGe：C）合金含有区域，其中退火后SiGe：C合金的晶格常数大于退火之前的SiGe：C合金。该方法可用于制备包括金属氧化物半导体场效应晶体管（MOSFET）器件的制品。

2. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

3. 发明申请

US20070238276A1 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US20070238276A1
公开(公告)日：2007-10-11
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

4. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

5. 发明申请

US20070164356A1 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US20070164356A1
公开(公告)日：2007-07-19
申请号：US11332564
申请日：2006-01-13
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

6. 发明申请

US20060275961A1 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20060275961A1
公开(公告)日：2006-12-07
申请号：US11492271
申请日：2006-07-25
申请人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
发明人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

7. 发明申请

US20050093100A1 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US20050093100A1
公开(公告)日：2005-05-05
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/762 , H01L27/12 , H01L27/144 , H01L31/0232 , H01L31/028 , H01L31/0352 , H01L31/105 , H01L31/18 , H01L31/117
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

8. 发明申请

US20070257315A1 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors 审中-公开
标题翻译：离子注入与原位或非原位热处理相结合，用于改进的场效应晶体管
公开(公告)号：US20070257315A1
公开(公告)日：2007-11-08
申请号：US11417846
申请日：2006-05-04
申请人： Stephen Bedell , Joel De Souza , Zhibin Ren , Alexander Reznicek , Devendra Sadana , Katherine Saenger , Ghavam Shahidi
发明人： Stephen Bedell , Joel De Souza , Zhibin Ren , Alexander Reznicek , Devendra Sadana , Katherine Saenger , Ghavam Shahidi
IPC分类号： H01L21/8234
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源极/漏极（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

9. 发明申请

US20060154442A1 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide 有权
标题翻译：使用亲水硅表面的准疏水Si-Si晶片结合和界面结合氧化物的溶解
公开(公告)号：US20060154442A1
公开(公告)日：2006-07-13
申请号：US11031165
申请日：2005-01-07
申请人： Joel de Souza , John Ott , Alexander Reznicek , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , John Ott , Alexander Reznicek , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/46
CPC分类号： H01L21/187 , H01L21/76251
摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.
摘要翻译：本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

10. 发明申请

US20100006985A1 FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT 失效
标题翻译：通过氧化硅与工程化孔隙度梯度形成SOI
公开(公告)号：US20100006985A1
公开(公告)日：2010-01-14
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

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