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1. 发明申请

US20080206965A1 STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY 审中-公开
标题翻译：通过从Si（1-x-y）GexCy合金中制备碳制成的应变硅
公开(公告)号：US20080206965A1
公开(公告)日：2008-08-28
申请号：US11679308
申请日：2007-02-27
申请人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Oleg Gluschenkov , Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20
CPC分类号： H01L29/4983 , H01L21/02529 , H01L21/02532 , H01L21/02667 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices.
摘要翻译：本发明公开了一种制备应变硅的方法，包括退火邻近硅区的碳掺杂硅 - 锗（SiGe：C）合金含有区域，其中退火后SiGe：C合金的晶格常数大于退火之前的SiGe：C合金。该方法可用于制备包括金属氧化物半导体场效应晶体管（MOSFET）器件的制品。

2. 发明申请

US20070238276A1 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US20070238276A1
公开(公告)日：2007-10-11
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

3. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

4. 发明申请

US20080217697A1 CONTROL OF POLY-Si DEPLETION IN CMOS VIA GAS PHASE DOPING 失效
标题翻译：通过气相放电的CMOS中的多硅沉淀的控制
公开(公告)号：US20080217697A1
公开(公告)日：2008-09-11
申请号：US12127171
申请日：2008-05-27
申请人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

5. 发明授权

US07655551B2 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US07655551B2
公开(公告)日：2010-02-02
申请号：US12127171
申请日：2008-05-27
申请人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了包括例如nFET和/或pFET的CMOS结构，其利用本文所述的气相掺杂技术制造。

6. 发明授权

US07473626B2 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US07473626B2
公开(公告)日：2009-01-06
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

7. 发明授权

US07888197B2 Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer 有权
标题翻译：使用牺牲应力层形成具有掺杂玻璃盒层的应力SOI FET的方法
公开(公告)号：US07888197B2
公开(公告)日：2011-02-15
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer is then removed to expose the stressed SOI layer. Field effect transistors can then be formed in the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法。在这种方法中，形成SOI衬底，其包括（i）通过（iii）包含掺杂硅酸盐玻璃层的掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层。牺牲应力层沉积在SOI衬底上以覆盖SOI层。然后将沟槽蚀刻穿过牺牲应力层并进入SOI层。用牺牲应力层将SOI衬底充分加热，使玻璃层软化，牺牲应力层松弛，从而向SOI层施加应力以形成受应力的SOI层。然后用电介质材料填充受应力的SOI层中的沟槽，以形成接触应力SOI层的外围边缘的沟槽隔离区，沟槽隔离区域从受应力的SOI层的主表面向BOX层向下延伸。然后去除牺牲应力层以暴露受应力的SOI层。然后可以在受应力的SOI层中形成场效应晶体管。

8. 发明授权

US07838932B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 有权
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07838932B2
公开(公告)日：2010-11-23
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L29/76257
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

9. 发明授权

US07598147B2 Method of forming CMOS with Si:C source/drain by laser melting and recrystallization 有权
标题翻译：通过激光熔融和重结晶用Si：C源极/漏极形成CMOS的方法
公开(公告)号：US07598147B2
公开(公告)日：2009-10-06
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持半导体结构的结构完整性。

10. 发明授权

US07473594B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 失效
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07473594B2
公开(公告)日：2009-01-06
申请号：US11459730
申请日：2006-07-25
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

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