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1. 发明申请

US20100006985A1 FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT 失效
标题翻译：通过氧化硅与工程化孔隙度梯度形成SOI
公开(公告)号：US20100006985A1
公开(公告)日：2010-01-14
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

2. 发明授权

US07772096B2 Formation of SOI by oxidation of silicon with engineered porosity gradient 失效
标题翻译：通过工程化孔隙度梯度的硅氧化形成SOI
公开(公告)号：US07772096B2
公开(公告)日：2010-08-10
申请号：US12170459
申请日：2008-07-10
申请人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
发明人： Joel P. DeSouza , Keith E. Fogel , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76245
摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.
摘要翻译：提供了一种制造绝缘体上硅衬底的方法。这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层从底层半导体区域。可以在非高p型掺杂外延层同时退火的同时执行这种处理。

3. 发明授权

US07968459B2 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors 有权
标题翻译：离子注入与原位或非原位热处理相结合，用于改进的场效应晶体管
公开(公告)号：US07968459B2
公开(公告)日：2011-06-28
申请号：US12128040
申请日：2008-05-28
申请人： Stephen W. Bedell , Joel P. DeSouza , Zhibin Ren , Alexander Reznicek , Devandra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
发明人： Stephen W. Bedell , Joel P. DeSouza , Zhibin Ren , Alexander Reznicek , Devandra K. Sadana , Katherine L. Saenger , Ghavam Shahidi
IPC分类号： H01L21/44
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源/漏（S / D）区域的潜在问题）的方法，以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

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