专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07470595B2 Oxidizing a metal layer for a dielectric having a platinum electrode 有权
标题翻译：氧化具有铂电极的电介质的金属层
公开(公告)号：US07470595B2
公开(公告)日：2008-12-30
申请号：US11497344
申请日：2006-08-02
申请人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
发明人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
IPC分类号： H01L21/20 , H01L21/76
CPC分类号： H01L28/65 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.
摘要翻译：紧密接触层设置在半导体衬底上，紧密接触层由选自耐火金属，难熔金属合金，难熔金属氮化物和难熔金属的氮化硅组成的组中的一种材料制成。氧化物表面层设置在紧密接触层的表面上，氧化物表面层由构成紧密接触层的材料的氧化物制成。第一导电层设置在氧化物表面层的表面上，第一导电层由含有铂族的铂族或合金制成。当在紧密接触层上形成由诸如铂族基团的金属制成的导电层时，可以防止覆盖和形态的劣化。

2. 发明申请

US20060286744A1 Semiconductor device suitable for forming conductive film such as platinum with good coverage, and its manufacture 有权
公开(公告)号：US20060286744A1
公开(公告)日：2006-12-21
申请号：US11497344
申请日：2006-08-02
申请人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
发明人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
IPC分类号： H01L21/8242
CPC分类号： H01L28/65 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.

3. 发明授权

US07102189B2 Semiconductor device suitable for forming conductive film such as platinum with good coverage, and its manufacture 有权
标题翻译：半导体器件适用于形成具有良好覆盖性的铂等导电膜及其制造
公开(公告)号：US07102189B2
公开(公告)日：2006-09-05
申请号：US10745967
申请日：2003-12-29
申请人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
发明人： Nobuyuki Nishikawa , Hiroshi Minakata , Kouji Tsunoda , Eiji Yoshida
IPC分类号： H01L27/108
CPC分类号： H01L28/65 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.
摘要翻译：紧密接触层设置在半导体衬底上，紧密接触层由选自耐火金属，难熔金属合金，难熔金属氮化物和难熔金属的氮化硅组成的组中的一种材料制成。氧化物表面层设置在紧密接触层的表面上，氧化物表面层由构成紧密接触层的材料的氧化物制成。第一导电层设置在氧化物表面层的表面上，第一导电层由含有铂族的铂族或合金制成。当在紧密接触层上形成由诸如铂族基团的金属制成的导电层时，可以防止覆盖和形态的劣化。

4. 发明授权

US07265401B2 Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
标题翻译：具有高介电常数栅极绝缘层的半导体器件及其制造方法
公开(公告)号：US07265401B2
公开(公告)日：2007-09-04
申请号：US11148317
申请日：2005-06-09
申请人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
发明人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/823857 , H01L29/513
摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.
摘要翻译：半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。

5. 发明授权

US5459821A Method and apparatus for generating a free-form surface 失效
标题翻译：用于产生自由曲面的方法和装置
公开(公告)号：US5459821A
公开(公告)日：1995-10-17
申请号：US967467
申请日：1992-10-23
申请人： Shigeru Kuriyama , Hiroshi Minakata , Naoki Urano , Kazuya Shimizu
发明人： Shigeru Kuriyama , Hiroshi Minakata , Naoki Urano , Kazuya Shimizu
IPC分类号： B24B5/18 , B24B5/313 , G06T17/30 , G06T17/20
CPC分类号： G06T17/30
摘要： A method for generating a multisided patch in which the expression form of each boundary curve and topology of the curve network can freely be set, curve formulae can be simply input, and high continuity. By inputting data of boundary curves to multisided patch generator via editing means which generates and edits curves, and blending sweep surfaces in two stages, a free-form surface is generated as a surface interpolating them. That is, data of a plurality of boundary curves is inputted to multisided patch generator, each given curve is swept by sweeping means along the curves intersecting it to generate surfaces, and the surfaces are blended by blending means in two stages, thereby generating a free-form surface. Since the surface formulae can be defined on the basis of the curve formulae of the boundaries, topology of the curve network and the descriptive form of each curve can freely be set, so that the boundary curve formulae of a multisided patch can be simply input by directly drawing the curve shapes on defined two-dimensional planes. In addition, geometric continuity of the generated surface is high because continuity of the given curves is high.
摘要翻译：一种生成可以自由设置每个边界曲线的表达形式和曲线网络拓扑的多区块的方法，可以简单地输入曲线公式，并具有高连续性。通过将生成和编辑曲线的编辑装置的边界曲线的数据输入到多段贴片发生器，并且将扫描表面混合在两个阶段中，生成自由曲面作为表面内插它们。也就是说，多边界曲线的数据被输入到多片贴片发生器，每个给定的曲线被扫描装置沿着与其相交的曲线扫过以产生表面，并且表面通过混合装置分两个阶段共混，从而产生一个自由形状表面。由于表面公式可以根据边界的曲线公式定义，曲线网络的拓扑结构和每个曲线的描述形式可以自由设置，从而可以简单地输入多维贴片的边界曲线公式直接在定义的二维平面上绘制曲线形状。此外，由于给定曲线的连续性高，所以产生的表面的几何连续性很高。

6. 发明授权

US07741684B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07741684B2
公开(公告)日：2010-06-22
申请号：US11183756
申请日：2005-07-19
申请人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
发明人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/32055 , H01L29/517 , H01L29/6659
摘要： The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7
摘要翻译：半导体器件包括栅极绝缘膜，该栅极绝缘膜包括在半导体衬底上形成的Hf x Al 1-x O y（0.7

7. 发明申请

US20060214244A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214244A1
公开(公告)日：2006-09-28
申请号：US11198166
申请日：2005-08-08
申请人： Hiroshi Minakata
发明人： Hiroshi Minakata
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/31122 , H01L29/517 , H01L29/6659
摘要： In the method for fabricating a semiconductor device, a polysilicon film is patterned to form a gate electrode 16, and a high dielectric constant insulating film 14 on a silicon substrate 10 and a device isolation film 12 on both sides of the gate electrode 16 is removed by dry etching using plasmas of a mixed gas of a base protection gas which combines with silicon to form a protection layer for protecting the silicon substrate 10 and the device isolation film 12, and an etching gas for etching the high dielectric constant insulating film 14.
摘要翻译：在制造半导体器件的方法中，对多晶硅膜进行构图以形成栅电极16，并且去除在硅衬底10上的高介电常数绝缘膜14和位于栅电极16两侧的器件隔离膜12 通过使用与硅组合的基底保护气体的混合气体的等离子体进行干蚀刻以形成用于保护硅衬底10和器件隔离膜12的保护层，以及用于蚀刻高介电常数绝缘膜14的蚀刻气体。

8. 发明授权

US06946351B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06946351B2
公开(公告)日：2005-09-20
申请号：US10768090
申请日：2004-02-02
申请人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
发明人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
IPC分类号： H01L21/316 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/51 , H01L29/78 , H01L31/0328 , H01L31/113
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/32055 , H01L29/517 , H01L29/6659
摘要： The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1−xOy (0.7
摘要翻译：该半导体器件包括栅极绝缘膜，该栅极绝缘膜包括第一绝缘膜，其具有第一绝缘膜和第二绝缘膜，形成在半导体衬底上，以及与形成在第一电介质膜上的第一电介质膜不同的第二电介质膜; 以及形成在栅极绝缘膜上并包括多晶硅膜的栅电极，从而防止了在形成多晶硅膜的过程中多晶硅膜的局部异常生长，并且栅极漏电流可以大大降低。

9. 发明申请

US20060172498A1 Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
标题翻译：具有高介电常数栅极绝缘层的半导体器件及其制造方法
公开(公告)号：US20060172498A1
公开(公告)日：2006-08-03
申请号：US11148317
申请日：2005-06-09
申请人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
发明人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/823857 , H01L29/513
摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.
摘要翻译：半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。

10. 发明申请

US20050142715A1 Semiconductor device with high dielectric constant insulator and its manufacture 审中-公开
标题翻译：具有高介电常数绝缘子的半导体器件及其制造
公开(公告)号：US20050142715A1
公开(公告)日：2005-06-30
申请号：US10973449
申请日：2004-10-27
申请人： Tsunehisa Sakoda , Yoshihiro Sugiyama , Masaomi Yamaguchi , Hiroshi Minakata
发明人： Tsunehisa Sakoda , Yoshihiro Sugiyama , Masaomi Yamaguchi , Hiroshi Minakata
IPC分类号： C23C16/40 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L29/51 , H01L29/78
CPC分类号： H01L21/022 , C23C16/40 , C23C16/405 , H01L21/02164 , H01L21/0217 , H01L21/02172 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A semiconductor device has: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a high dielectric constant insulating film including a first oxide layer formed above the silicon oxide layer and made of a high dielectric constant film having a dielectric constant higher than silicon oxide and a first nitride layer formed above the first oxide layer and made of nitride having an oxygen intercepting capability, or a high dielectric constant insulating film including a first oxide film formed on the silicon oxide layer, a second oxide layer formed on the first oxide layer and a third oxide layer formed on the second oxide layer, the first and third oxide layers having an oxygen diffusion coefficient smaller than the second oxide layer; and a gate electrode formed on the high dielectric constant insulating layer and made of oxidizable material.
摘要翻译：半导体器件具有：硅衬底; 形成在所述硅衬底的表面上的氧化硅层; 一种高介电常数绝缘膜，包括形成在氧化硅层之上并由介电常数高于氧化硅的高介电常数膜构成的第一氧化物层和形成在第一氧化物层上方的第一氮化物层，并由具有或具有在氧化硅层上形成的第一氧化膜的高介电常数绝缘膜，形成在第一氧化物层上的第二氧化物层和形成在第二氧化物层上的第三氧化物层，第一氧化物层和第三氧化物层具有比第二氧化物层小的氧扩散系数的层; 以及形成在高介电常数绝缘层上并由可氧化材料制成的栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式