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1. 发明申请

US20050247988A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050247988A1
公开(公告)日：2005-11-10
申请号：US11183756
申请日：2005-07-19
申请人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
发明人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
IPC分类号： H01L21/316 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/51 , H01L29/78 , H01L31/0328 , H01L31/113
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/32055 , H01L29/517 , H01L29/6659
摘要： The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7
摘要翻译：该半导体器件包括栅极绝缘膜，该栅极绝缘膜包括第一绝缘膜，其具有第一绝缘膜和第二绝缘膜，形成在半导体衬底上，以及与形成在第一电介质膜上的第一电介质膜不同的第二电介质膜; 以及形成在栅极绝缘膜上并包括多晶硅膜的栅电极，从而防止了在形成多晶硅膜的过程中多晶硅膜的局部异常生长，并且栅极漏电流可以大大降低。

2. 发明授权

US5094978A Method of patterning a transparent conductor 失效
标题翻译：绘制透明导体的方法
公开(公告)号：US5094978A
公开(公告)日：1992-03-10
申请号：US554367
申请日：1990-07-19
申请人： Shinji Miyagaki , Seigen Ri
发明人： Shinji Miyagaki , Seigen Ri
IPC分类号： H01L21/302 , H01L21/306 , H01L27/146 , H01L31/18
CPC分类号： H01L31/1884 , Y02E10/50 , Y10S438/963
摘要： A method of forming a pattern of a transparent conducting film such as an indium tin oxide film, formed on the surface of a substrate including Si and being heated. A two-step etching method is employed, in which the transparent conducting film is wet-etched by an aqueous solution of a halogenide and thereafter an interfacial reacted layer generated at the interface of the transparent conducting film and substrate including Si is etched by a plasma etching method using a halogen.

3. 发明授权

US06188090B1 Semiconductor device having a heteroepitaxial substrate 失效
标题翻译：具有异质外延衬底的半导体器件
公开(公告)号：US06188090B1
公开(公告)日：2001-02-13
申请号：US09026915
申请日：1998-02-20
申请人： Shinji Miyagaki , Takashi Eshita , Satoshi Ohkubo , Kazuaki Takai
发明人： Shinji Miyagaki , Takashi Eshita , Satoshi Ohkubo , Kazuaki Takai
IPC分类号： H01L310328
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02494 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L29/66462
摘要： A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.
摘要翻译：一种制造化合物半导体器件的方法包括以下步骤：在Si衬底的表面上沉积第一III-V族化合物半导体层，同时将Si衬底的温度保持在第一温度，沉积第二组III-V族化合物半导体层，同时保持基板的温度处于第二较高温度，并且在第二组III-V族化合物半导体层上沉积第三组III-V族化合物半导体层，同时保持第在比所述第二温度高的第三温度下的衬底的温度，其中第二组III-V族化合物半导体层含有Al。

4. 发明授权

US5093564A Photosensor having an amorphous silicon photoabsorption layer 失效
标题翻译：具有非晶硅摄影层的光电传感器
公开(公告)号：US5093564A
公开(公告)日：1992-03-03
申请号：US610590
申请日：1990-11-08
申请人： Shinji Miyagaki , Seigen Ri
发明人： Shinji Miyagaki , Seigen Ri
IPC分类号： H01L31/10 , H01L27/146
CPC分类号： H01L27/14643
摘要： A photosensor comprises an insulator layer, a first electrode on the insulator layer for collecting first type carriers formed upon incidence of optical radiation, the first electrode being segmented into a plurality of pixel electrodes separated from each other by a gap, a first silicon carbide layer provided on the insulator layer to cover the plurality of pixel electrodes including the gap separating adjacent pixel electrodes, an optical absorption layer of amorphous silicon provided on the silicon carbide layer continuously such that the amorphous silicon layer extends over the plurality of pixel electrodes and the gap between adjacent pixel electrodes, the optical absorption layer producing the first type carriers and second type carriers having opposing polarity to the first type carriers upon incidence of the optical radiation, a second silicon carbide layer provided on the amorphous silicon layer for protecting the optical absorption layer from chemical reaction, and a second electrode of a transparent material provided on the silicon carbide layer for collecting the second type carriers produced in the optical absorption layer, wherein the first silicon carbide layer is doped to have a conductivity that enables formation of an electric field equal to or larger than about 4 volts/.mu.m in magnitude in the amorphous silicon layer and such that the conductivity is equal to or smaller than the conductivity of the amorphous silicon layer.

5. 发明授权

US5066612A Method of forming wiring of a semiconductor device 失效
标题翻译：形成半导体器件布线的方法
公开(公告)号：US5066612A
公开(公告)日：1991-11-19
申请号：US637152
申请日：1991-01-03
申请人： Takayuki Ohba , Shinji Miyagaki , Tatsushi Hara , Kenji Morishita , Seiichi Suzuki , Seigen Ri
发明人： Takayuki Ohba , Shinji Miyagaki , Tatsushi Hara , Kenji Morishita , Seiichi Suzuki , Seigen Ri
IPC分类号： H01L21/768 , H01L23/485 , H01L21/44 , H01L21/48
CPC分类号： H01L23/485 , H01L21/76879 , H01L2924/0002
摘要： In the course of a production of a semiconductor device with a multilayer insulating layer, when a contact hole is opened in the multilayer insulating layer, an insulating layer activating a metal selective vapor-growth appears at the side wall of the contact hole. A thin metal (e.g., tungsten) layer is selectively deposited in the contact hole. In another case, another metal layer appears within the contact hole. An insulating film preventing a metal selective vapor-growth is deposited over the whole surface of the side wall of the contact hole, the metal layer and a top surface of the multilayer insulating layer, and is anisotropically etched to leave a portion of the film lying on the side wall only as a side wall insulating film. The contact hole is completely filled with another metal (tungsten) by a selective vapor-growth method, to flatten an exposed surface, and then a conductor (e.g., aluminum) line layer is formed on the metal layer in the contact hole and the multilayer insulating layer, to thereby complete the wiring structure of the semiconductor device.
摘要翻译：在制造具有多层绝缘层的半导体器件的过程中，当多层绝缘层中的接触孔开放时，在接触孔的侧壁处出现激活金属选择性气相生长的绝缘层。在接触孔中选择性地沉积薄金属（例如钨）层。在另一种情况下，另一金属层出现在接触孔内。防止金属选择性气相生长的绝缘膜沉积在接触孔的侧壁，金属层和多层绝缘层的顶表面的整个表面上，并被各向异性地蚀刻以使膜的一部分位于在侧壁上仅作为侧壁绝缘膜。接触孔通过选择性气相生长法完全填充另一种金属（钨），使露出的表面变平，然后在接触孔中的金属层上形成导体（例如，铝）线层，多层绝缘层，从而完成半导体器件的布线结构。

6. 发明授权

US07741684B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07741684B2
公开(公告)日：2010-06-22
申请号：US11183756
申请日：2005-07-19
申请人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
发明人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/32055 , H01L29/517 , H01L29/6659
摘要： The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1-xOy (0.7
摘要翻译：半导体器件包括栅极绝缘膜，该栅极绝缘膜包括在半导体衬底上形成的Hf x Al 1-x O y（0.7

7. 发明授权

US06946351B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06946351B2
公开(公告)日：2005-09-20
申请号：US10768090
申请日：2004-02-02
申请人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
发明人： Chikako Yoshida , Hiroshi Minakata , Masaomi Yamaguchi , Shinji Miyagaki , Yasuyuki Tamura
IPC分类号： H01L21/316 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/51 , H01L29/78 , H01L31/0328 , H01L31/113
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/32055 , H01L29/517 , H01L29/6659
摘要： The semiconductor device comprises a gate insulating film including a first dielectric film of HfxAl1−xOy (0.7
摘要翻译：该半导体器件包括栅极绝缘膜，该栅极绝缘膜包括第一绝缘膜，其具有第一绝缘膜和第二绝缘膜，形成在半导体衬底上，以及与形成在第一电介质膜上的第一电介质膜不同的第二电介质膜; 以及形成在栅极绝缘膜上并包括多晶硅膜的栅电极，从而防止了在形成多晶硅膜的过程中多晶硅膜的局部异常生长，并且栅极漏电流可以大大降低。

8. 发明授权

US5834362A Method of making a device having a heteroepitaxial substrate 失效
标题翻译：制造具有异质外延衬底的器件的方法
公开(公告)号：US5834362A
公开(公告)日：1998-11-10
申请号：US619249
申请日：1996-03-21
申请人： Shinji Miyagaki , Takashi Eshita , Satoshi Ohkubo , Kazuaki Takai
发明人： Shinji Miyagaki , Takashi Eshita , Satoshi Ohkubo , Kazuaki Takai
IPC分类号： H01L21/20 , H01L21/335 , H01L21/338 , H01L21/331 , H01L21/36
CPC分类号： H01L21/02461 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02494 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L29/66462
摘要： A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.
摘要翻译：一种制造化合物半导体器件的方法包括以下步骤：在Si衬底的表面上沉积第一III-V族化合物半导体层，同时将Si衬底的温度保持在第一温度，沉积第二组III-V族化合物半导体层，同时保持基板的温度处于第二较高温度，并且在第二组III-V族化合物半导体层上沉积第三组III-V族化合物半导体层，同时保持第在比所述第二温度高的第三温度下的衬底的温度，其中第二组III-V族化合物半导体层含有Al。

9. 发明授权

US5492860A Method for growing compound semiconductor layers 失效
标题翻译：生长化合物半导体层的方法
公开(公告)号：US5492860A
公开(公告)日：1996-02-20
申请号：US47202
申请日：1993-04-16
申请人： Satoshi Ohkubo , Shinji Miyagaki
发明人： Satoshi Ohkubo , Shinji Miyagaki
IPC分类号： H01L21/20 , H01L21/203
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02463 , H01L21/02505 , H01L21/02546 , Y10S148/017 , Y10S438/933
摘要： A method of growing a layer of a III-V compound semiconductor on a silicon substrate comprises an oxide layer removing step of removing an oxide layer on a surface of the silicon substrate at a first temperature, a low-temperature grown layer forming step of forming a low-temperature grown layer of the III-V compound semiconductor on the silicon substrate while introducing a source gas for Group III and a source gas for Group V at a second temperature lower than the first temperature, and a single crystal layer growing step of growing a single crystal layer of the Group III-V compound semiconductor on the low-temperature grown layer while introducing the source gas for Group III and the source gas for Group V at a third temperature higher than the second temperature and lower than the first temperature. The introduction of the source gas for Group V being started between the oxide layer removing step and the low-temperature grown layer forming step and at a predetermined temperature lower than the first temperature and higher than the third temperature, at which the first temperature arrives while being lowered to the second temperature. The surface of a silicone substrate is prevented from contamination before the formation of the low-temperature grown layer. A III-V compound semiconductor layer which is superior in crystal perfection and surface morphology can be formed.
摘要翻译：在硅衬底上生长III-V族化合物半导体层的方法包括在第一温度下去除硅衬底表面上的氧化物层的氧化物层去除步骤，形成第一温度的低温生长层形成步骤在第二温度低于第一温度的同时，在硅衬底上引入III-V族化合物半导体的低温生长层，同时引入第III族源气体和V族源气体;以及单晶层生长步骤在低温生长层上生长第III-V族化合物半导体的单晶层，同时在比第二温度高且低于第一温度的第三温度下引入用于组III的源气体和V族源气体。在氧化物层去除步骤和低温生长层形成步骤之间并且在比第一温度低的第一温度和高于第一温度到达的第三温度的预定温度下开始引入用于V组的源气体，降至第二温度。在形成低温生长层之前，防止硅树脂基材的表面被污染。可以形成晶体完整性和表面形态优异的III-V族化合物半导体层。

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