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1. 发明授权

US07927941B2 Method of fabricating field effect transistors with different gate widths 有权
标题翻译：制造栅极宽度不同的场效晶体管的方法
公开(公告)号：US07927941B2
公开(公告)日：2011-04-19
申请号：US12817508
申请日：2010-06-17
申请人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
发明人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
IPC分类号： H01L21/336 , H01L27/148
CPC分类号： H01L21/823842 , H01L21/82385
摘要： Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
摘要翻译：四个区域（窄NMOS区域，宽NMOS区域，宽PMOS区域和窄PMOS区域）限定在半导体衬底上。然后，在半导体衬底上依次形成栅极绝缘膜和多晶硅膜之后，在宽NMOS区域中将n型杂质引入到多晶硅膜中。接下来，通过构图多晶硅膜，在四个区域中形成栅电极。然后，在窄NMOS区域和宽NMOS区域中的栅电极中引入n型杂质。结果，窄NMOS区域中的栅电极的杂质浓度变得比宽NMOS区域中的栅电极的杂质浓度低。

2. 发明申请

US20060172498A1 Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
标题翻译：具有高介电常数栅极绝缘层的半导体器件及其制造方法
公开(公告)号：US20060172498A1
公开(公告)日：2006-08-03
申请号：US11148317
申请日：2005-06-09
申请人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
发明人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/823857 , H01L29/513
摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.
摘要翻译：半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。

3. 发明申请

US20050142715A1 Semiconductor device with high dielectric constant insulator and its manufacture 审中-公开
标题翻译：具有高介电常数绝缘子的半导体器件及其制造
公开(公告)号：US20050142715A1
公开(公告)日：2005-06-30
申请号：US10973449
申请日：2004-10-27
申请人： Tsunehisa Sakoda , Yoshihiro Sugiyama , Masaomi Yamaguchi , Hiroshi Minakata
发明人： Tsunehisa Sakoda , Yoshihiro Sugiyama , Masaomi Yamaguchi , Hiroshi Minakata
IPC分类号： C23C16/40 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L29/51 , H01L29/78
CPC分类号： H01L21/022 , C23C16/40 , C23C16/405 , H01L21/02164 , H01L21/0217 , H01L21/02172 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A semiconductor device has: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a high dielectric constant insulating film including a first oxide layer formed above the silicon oxide layer and made of a high dielectric constant film having a dielectric constant higher than silicon oxide and a first nitride layer formed above the first oxide layer and made of nitride having an oxygen intercepting capability, or a high dielectric constant insulating film including a first oxide film formed on the silicon oxide layer, a second oxide layer formed on the first oxide layer and a third oxide layer formed on the second oxide layer, the first and third oxide layers having an oxygen diffusion coefficient smaller than the second oxide layer; and a gate electrode formed on the high dielectric constant insulating layer and made of oxidizable material.
摘要翻译：半导体器件具有：硅衬底; 形成在所述硅衬底的表面上的氧化硅层; 一种高介电常数绝缘膜，包括形成在氧化硅层之上并由介电常数高于氧化硅的高介电常数膜构成的第一氧化物层和形成在第一氧化物层上方的第一氮化物层，并由具有或具有在氧化硅层上形成的第一氧化膜的高介电常数绝缘膜，形成在第一氧化物层上的第二氧化物层和形成在第二氧化物层上的第三氧化物层，第一氧化物层和第三氧化物层具有比第二氧化物层小的氧扩散系数的层; 以及形成在高介电常数绝缘层上并由可氧化材料制成的栅电极。

4. 发明申请

US20070232004A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070232004A1
公开(公告)日：2007-10-04
申请号：US11518317
申请日：2006-09-11
申请人： Tsunehisa Sakoda , Kazuto Ikeda
发明人： Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28202 , H01L29/517
摘要： A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.
摘要翻译：能够抑制阈值偏移的半导体器件和半导体器件的制造方法。在高介电常数绝缘膜上形成用于防止金属元素从高介电常数绝缘膜向上层扩散的扩散阻挡膜。因此，可以防止金属元素从高介电常数绝缘膜扩散到上层。结果，可以在绝缘膜和栅电极之间的边界附近抑制金属元件与栅电极中的Si元素之间的反应和接合。

5. 发明申请

US20060214243A1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US20060214243A1
公开(公告)日：2006-09-28
申请号：US11190911
申请日：2005-07-28
申请人： Tsunehisa Sakoda , Masaomi Yamaguchi , Hiroshi Minakata , Yoshihiro Sugita , Kazuto Ikeda
发明人： Tsunehisa Sakoda , Masaomi Yamaguchi , Hiroshi Minakata , Yoshihiro Sugita , Kazuto Ikeda
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.

6. 发明授权

US07893508B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07893508B2
公开(公告)日：2011-02-22
申请号：US11518317
申请日：2006-09-11
申请人： Tsunehisa Sakoda , Kazuto Ikeda
发明人： Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L29/94
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28202 , H01L29/517
摘要： A semiconductor device capable of suppressing a threshold shift and a manufacturing method of the semiconductor device. On a high dielectric constant insulating film, a diffusion barrier film for preventing the diffusion of metal elements from the high dielectric constant insulating film to an upper layer is formed. Therefore, the diffusion of the metal elements from the high dielectric constant insulating film to the upper layer can be prevented. As a result, a reaction and bonding between the metal elements and a Si element in a gate electrode can be suppressed near a boundary between an insulating film and the gate electrode.
摘要翻译：能够抑制阈值偏移的半导体器件和半导体器件的制造方法。在高介电常数绝缘膜上形成用于防止金属元素从高介电常数绝缘膜向上层扩散的扩散阻挡膜。因此，可以防止金属元素从高介电常数绝缘膜扩散到上层。结果，可以在绝缘膜和栅电极之间的边界附近抑制金属元件与栅电极中的Si元素之间的反应和接合。

7. 发明授权

US07768039B2 Field effect transistors with different gate widths 有权
标题翻译：具有不同栅极宽度的场效应晶体管
公开(公告)号：US07768039B2
公开(公告)日：2010-08-03
申请号：US11236509
申请日：2005-09-28
申请人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
发明人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
IPC分类号： H01L31/112
CPC分类号： H01L21/823842 , H01L21/82385
摘要： Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
摘要翻译：四个区域（窄NMOS区域，宽NMOS区域，宽PMOS区域和窄PMOS区域）限定在半导体衬底上。然后，在半导体衬底上依次形成栅极绝缘膜和多晶硅膜之后，在宽NMOS区域中将n型杂质引入到多晶硅膜中。接下来，通过构图多晶硅膜，在四个区域中形成栅电极。然后，在窄NMOS区域和宽NMOS区域中的栅电极中引入n型杂质。结果，窄NMOS区域中的栅电极的杂质浓度变得比宽NMOS区域中的栅电极的杂质浓度低。

8. 发明授权

US07265401B2 Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
标题翻译：具有高介电常数栅极绝缘层的半导体器件及其制造方法
公开(公告)号：US07265401B2
公开(公告)日：2007-09-04
申请号：US11148317
申请日：2005-06-09
申请人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
发明人： Masaomi Yamaguchi , Hiroshi Minakata , Tsunehisa Sakoda , Kazuto Ikeda
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/823857 , H01L29/513
摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.
摘要翻译：半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。

9. 发明申请

US20060292782A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060292782A1
公开(公告)日：2006-12-28
申请号：US11236509
申请日：2005-09-28
申请人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
发明人： Hiroshi Nomura , Takashi Saiki , Tsunehisa Sakoda
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/82385
摘要： Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.
摘要翻译：四个区域（窄NMOS区域，宽NMOS区域，宽PMOS区域和窄PMOS区域）限定在半导体衬底上。然后，在半导体衬底上依次形成栅极绝缘膜和多晶硅膜之后，在宽NMOS区域中将n型杂质引入到多晶硅膜中。接下来，通过构图多晶硅膜，在四个区域中形成栅电极。然后，在窄NMOS区域和宽NMOS区域中的栅电极中引入n型杂质。结果，窄NMOS区域中的栅电极的杂质浓度变得比宽NMOS区域中的栅电极的杂质浓度低。

10. 发明申请

US20100255668A1 Field effect transistors with different gate widths 有权
公开(公告)号：US20100255668A1
公开(公告)日：2010-10-07
申请号：US12817508
申请日：2010-06-17
申请人： Hiroshi NOMURA , Takashi Saiki , Tsunehisa Sakoda
发明人： Hiroshi NOMURA , Takashi Saiki , Tsunehisa Sakoda
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385
摘要： Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

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