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1. 发明授权

US06656752B1 Ion current density measuring method and instrument, and semiconductor device manufacturing method 失效
标题翻译：离子电流密度测量方法和仪器，以及半导体器件制造方法
公开(公告)号：US06656752B1
公开(公告)日：2003-12-02
申请号：US09890611
申请日：2001-10-11
申请人： Nobuyuki Mise , Tatehito Usui , Masato Ikegawa , Kazuo Nojiri , Kazuyuki Tsunokuni , Tetsuo Ono
发明人： Nobuyuki Mise , Tatehito Usui , Masato Ikegawa , Kazuo Nojiri , Kazuyuki Tsunokuni , Tetsuo Ono
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： A wafer is exposed to a plasma. Here, the wafer includes a semiconductor or a conductor 1 provided on an insulator 6, an insulator 2 formed thereon and having a region the thickness of which has been made locally thin, and a 2nd conductor 4 provided on the insulator 2, one of the semiconductor or the conductor 1 and the 2nd conductor 4 having a 1st region from the surface of which a substantially total solid angle is formed, the other having a 2nd region a solid angle formed from the surface of which is made smaller than the 1st region. Then, a voltage is applied to the semiconductor or the conductor 1 and the 2nd conductor 4 so as to measure a time elapsing until the insulator 2 undergoes a dielectric breakdown. Moreover, the ion current density is determined from an electric charge required therefor and an area exposed onto the surface of the 2nd conductor 4. Consequently, it becomes possible to measure, on the wafer, the current density of the ions launched into the wafer, thereby allowing the measuring method of the icon current density to be made suitable for the mass production.
摘要翻译：将晶片暴露于等离子体。这里，晶片包括设置在绝缘体6上的半导体或导体1，形成在其上的绝缘体2，其厚度局部变薄的区域和设置在绝缘体2上的第二导体4，半导体或导体1和第二导体4具有从其表面基本上具有总立体角的第一区域，另一个具有从其表面形成的立体角小于第一区域的第二区域。然后，向半导体或导体1和第二导体4施加电压，以测量直到绝缘体2经历介电击穿的时间。此外，离子电流密度由其所需的电荷和暴露于第二导体4的表面的面积确定。因此，可以在晶片上测量发射到晶片中的离子的电流密度，从而允许图标电流密度的测量方法适合于批量生产。

2. 发明授权

US5661061A Process for fabricating a semiconductor integrated circuit device having the multi-layered fin structure 失效
标题翻译：具有多层翅片结构的半导体集成电路器件的制造方法
公开(公告)号：US5661061A
公开(公告)日：1997-08-26
申请号：US411149
申请日：1995-03-27
申请人： Hirohisa Usuami , Kazuyuki Tsunokuni , Masayuki Kojima , Kazuo Nojiri , Keiji Okamoto
发明人： Hirohisa Usuami , Kazuyuki Tsunokuni , Masayuki Kojima , Kazuo Nojiri , Keiji Okamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.
摘要翻译：一种用于形成存储电极的上层翅片和下层翅片的方法，以及通过该方法制造的半导体集成电路器件。当通过使用第一掩模的干蚀刻方法顺序蚀刻两层多晶硅膜以形成上层翅片和下层翅片时，首先将上多晶硅膜图案化以形成以DRAM的存储单元的最小工作尺寸的上层翅片的间隙形成上层翅片。接下来，通过使用具有从第一掩模的图案自对准的图案放大的图案的第二掩模的干法蚀刻法形成下层翅片，使得其具有比上部的图案更大的水平尺寸层翅

3. 发明授权

US06340632B1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06340632B1
公开(公告)日：2002-01-22
申请号：US09585629
申请日：2000-06-02
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.
摘要翻译：绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到绝缘膜38。形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

4. 发明授权

US6077788A Method and apparatus for processing samples 失效
标题翻译：样品处理方法和装置
公开(公告)号：US6077788A
公开(公告)日：2000-06-20
申请号：US469998
申请日：1995-06-06
申请人： Yoshinao Kawasaki , Hironobu Kawahara , Yoshiaki Sato , Ryooji Fukuyama , Kazuo Nojiri , Yoshimi Torii
发明人： Yoshinao Kawasaki , Hironobu Kawahara , Yoshiaki Sato , Ryooji Fukuyama , Kazuo Nojiri , Yoshimi Torii
IPC分类号： C23F4/00 , H01L21/00 , H01L21/677 , H01L21/302 , C23F1/02
CPC分类号： H01L21/67161 , C23F4/00 , H01L21/67028 , H01L21/67745 , H01L21/67751
摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus, the samples being selectively etched through use of a resist mask), (b) for removing (ashing) the resist mask, (c) for wet-processing of the samples and (d) for dry-processing the samples. Samples are passed sequentially from a supply cassette (containing a plurality of samples) to the plasma etching apparatus, through the other apparatus and to a discharge cassette (which can hold a plurality of the samples). At least two of the samples can be processed simultaneously in a path from (and including), the plasma etching apparatus to (and including) the wet-processing structure.
摘要翻译：公开了用于处理样品的装置以及使用该装置的方法。该装置包括用于处理样品的处理装置（例如，等离子体蚀刻装置，通过使用抗蚀剂掩模选择性地蚀刻样品），（b）去除（灰化）抗蚀剂掩模，（c）处理样品和（d）干燥处理样品。样品从供应盒（含有多个样品）顺序地通过另一个装置和放电盒（可以容纳多个样品）通过等离子体蚀刻装置。至少两个样品可以在等离子体蚀刻装置（并且包括）湿法处理结构的路径中（并且包括）的同时进行处理。

5. 发明授权

US5917211A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5917211A
公开(公告)日：1999-06-29
申请号：US979543
申请日：1997-11-25
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/08 , H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

6. 发明授权

US5568277A Facsimile apparatus with improved control board arrangement 失效
标题翻译：具有改进的控制板布置的传真设备
公开(公告)号：US5568277A
公开(公告)日：1996-10-22
申请号：US464556
申请日：1995-06-06
申请人： Yasuhiro Hatano , Hajime Takayama , Yasushi Fukada , Kazuhiko Kurita , Kazuo Nojiri
发明人： Yasuhiro Hatano , Hajime Takayama , Yasushi Fukada , Kazuhiko Kurita , Kazuo Nojiri
IPC分类号： H04N1/00 , H04N1/12 , H04N1/193 , H04N1/04 , H04N1/191
CPC分类号： H04N1/00525 , H04N1/121 , H04N1/00885 , H04N1/193
摘要： The facsimile apparatus includes a casing with a handset arranged on a side thereof. Within the casing are disposed a network control section adjacent the handset and a power supply section opposite the network control section. A control board is arranged above the network control and power supply sections. The control board includes an analog signal control section adjacent to the network control section, a driving control section adjacent to the power supply section for driving a preselected electrical part, and a digital signal control section between the analog signal control section and the driving control section.
摘要翻译：该传真装置包括一个设置在其一侧的手机壳体。在壳体内设置有与手机相邻的网络控制部分和与网络控制部分相对的电源部分。控制板设置在网络控制和电源部分上方。控制板包括与网络控制部分相邻的模拟信号控制部分，与电源部分相邻的用于驱动预选电气部分的驱动控制部分，以及模拟信号控制部分和驱动控制部分之间的数字信号控制部分。

7. 发明授权

US5433789A Methods and apparatus for generating plasma, and semiconductor processing methods using mode restricted microwaves 失效
标题翻译：用于产生等离子体的方法和装置以及使用模式限制性微波的半导体处理方法
公开(公告)号：US5433789A
公开(公告)日：1995-07-18
申请号：US010051
申请日：1993-01-28
申请人： Yutaka Kakehi , Yoshinao Kawasaki , Keizo Suzuki , Kazuo Nojiri , Hiromichi Enami , Tetsunori Kaji , Seiichi Watanabe , Yoshifumi Ogawa
发明人： Yutaka Kakehi , Yoshinao Kawasaki , Keizo Suzuki , Kazuo Nojiri , Hiromichi Enami , Tetsunori Kaji , Seiichi Watanabe , Yoshifumi Ogawa
IPC分类号： C23C16/511 , H01J37/32 , C23C16/30 , H05H1/46
CPC分类号： H01J37/32229 , C23C16/511 , H01J37/32192 , H01J37/32266 , H01J37/32284
摘要： A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically-conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.
摘要翻译：等离子体处理装置具有微波从微波发生器传播到低压处理室中的等离子体形成区域的波导。波导具有大的横截面面积，以实现等离子体的大区域。等离子体的均匀性和稳定性通过抑制混合传播模式的模式限制器来改善，否则传播模式容易发生在宽波导中。模式限制器由导电分配器组成，其在等离子体形成区域之前将波导横截面分成子导轨阵列。

8. 发明授权

US07737023B2 Method of manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件和半导体集成电路器件的制造方法
公开(公告)号：US07737023B2
公开(公告)日：2010-06-15
申请号：US12194044
申请日：2008-08-19
申请人： Shouochi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
发明人： Shouochi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/0217 , H01L21/022 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835
摘要： In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
摘要翻译：在制造具有嵌入式互连结构的半导体集成电路器件的方法中，通过将导体膜嵌入形成在构成层间电介质膜的有机绝缘膜中的凹槽（例如沟槽或孔）中，并且包括有机硅氧烷作为通过在CF基气体/ N 2 / Ar气体中对有机绝缘膜进行等离子体干蚀刻来形成主要部件，凹槽，例如沟槽或孔，以抑制底部形成异常形状在有机绝缘膜上形成光致抗蚀剂膜之后，随后用光致抗蚀剂膜作为蚀刻掩模形成凹部。

9. 发明授权

US07419902B2 Method of manufacture of semiconductor integrated circuit 失效
标题翻译：半导体集成电路的制造方法
公开(公告)号：US07419902B2
公开(公告)日：2008-09-02
申请号：US11104441
申请日：2005-04-13
申请人： Shouochi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
发明人： Shouochi Uno , Atsushi Maekawa , Takashi Yunogami , Kazutami Tago , Kazuo Nojiri , Shuntaro Machida , Takafumi Tokunaga
IPC分类号： H01L21/4763
CPC分类号： H01L21/02126 , H01L21/0217 , H01L21/022 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835
摘要： In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.
摘要翻译：在制造具有嵌入式互连结构的半导体集成电路器件的方法中，通过将导体膜嵌入形成在构成层间电介质膜的有机绝缘膜中的凹槽（例如沟槽或孔）中，并且包括有机硅氧烷作为通过使有机绝缘膜在基于CF的气体/ N 2 / Ar气中进行等离子体干蚀刻来形成主要部件，凹槽，例如沟槽或孔，以便抑制在凹陷的底部形成异常形状，在有机绝缘膜上形成光致抗蚀剂膜，然后用光致抗蚀剂膜作为蚀刻掩模形成凹部。

10. 发明申请

US20070037292A1 Method and apparatus for processing samples 审中-公开
标题翻译：样品处理方法和装置
公开(公告)号：US20070037292A1
公开(公告)日：2007-02-15
申请号：US11585137
申请日：2006-10-24
申请人： Masayuki Kojima , Yoshimi Torii , Michimasa Hunabashi , Kazuyuki Suko , Takashi Yamada , Keizo Kuroiwa , Kazuo Nojiri , Yoshinao Kawasaki , Yoshiaki Sato , Ryooji Fukuyama , Hironobu Kawahara
发明人： Masayuki Kojima , Yoshimi Torii , Michimasa Hunabashi , Kazuyuki Suko , Takashi Yamada , Keizo Kuroiwa , Kazuo Nojiri , Yoshinao Kawasaki , Yoshiaki Sato , Ryooji Fukuyama , Hironobu Kawahara
IPC分类号： G01N1/00
CPC分类号： G01N1/32 , H01L21/67201 , H01L21/67742 , H01L21/67751 , Y10T436/25
摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g. plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
摘要翻译：公开了用于处理样品的装置以及使用该装置的方法。该设备包括用于处理样品（例如等离子体蚀刻设备）的处理设备（a），（b）用于除去由样品处理形成的残余腐蚀性化合物，（c）用于湿法处理样品，（d）处理样品。可以进行多个样品的湿法处理。湿式处理装置可以包括多个湿加工站。样品可以通过多个湿处理站串联通过，或者可以通过湿处理站并行通过。

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