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1. 发明授权

US08148682B2 Method and apparatus for pattern position and overlay measurement 有权
标题翻译：图案位置和重叠测量的方法和装置
公开(公告)号：US08148682B2
公开(公告)日：2012-04-03
申请号：US12648766
申请日：2009-12-29
申请人： Shoji Hotta , Norio Hasegawa
发明人： Shoji Hotta , Norio Hasegawa
IPC分类号： G01N23/00
CPC分类号： G03F7/70466 , G03F7/70633 , G06T7/60 , G06T2207/10061 , G06T2207/30148 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.
摘要翻译：使用成像装置图案的系统和方法来测量半导体制造工艺中的不同层之间的覆盖层，例如双重图案化工艺。通过扫描电子显微镜获得图案特征的图像。使用图像中的图案化层的图案特征的位置来确定图案化层的位置。基于所确定的图案位置，以向量形式确定每个图案形成层相对于其它图案特征或图案化层的相对位置。叠加误差是根据相对位置与设计或模拟参考值的比较来确定的。可以通过利用图案对称性以高精度和精度测量覆盖层。

2. 发明申请

US20070004189A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20070004189A1
公开(公告)日：2007-01-04
申请号：US11516762
申请日：2006-09-07
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/44
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

3. 发明授权

US06939649B2 Fabrication method of semiconductor integrated circuit device and mask 失效
标题翻译：半导体集成电路器件和掩模的制造方法
公开(公告)号：US06939649B2
公开(公告)日：2005-09-06
申请号：US10259397
申请日：2002-09-30
申请人： Shoji Hotta , Norio Hasegawa , Toshihiko Tanaka
发明人： Shoji Hotta , Norio Hasegawa , Toshihiko Tanaka
IPC分类号： G03F1/29 , G03F1/54 , G03F1/68 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F1/29
摘要： A method of fabrication of a semiconductor integrated circuit device uses a mark having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of light transmitted through the second light transmitting region relative to light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region. The second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first film and second is formed from a resist film.
摘要翻译：半导体集成电路器件的制造方法使用在掩模衬底的第一主表面上具有第一透光区域，设置在第一透光区域的周围的第二透光区域并允许反转透射通过第二透光区域的光相对于透过第一透光区域的光的相位，以及设置在第二透光区域周边的遮光区域。第二透光区域由沉积在掩模基板的第一主表面上的第一膜形成，所述遮光区域由通过所述第一膜沉积在掩模基板的第一主表面上的第二膜形成，并且至少所述第一膜和第二膜中的一个由抗蚀剂膜形成。

4. 发明申请

US20050118809A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050118809A1
公开(公告)日：2005-06-02
申请号：US10981662
申请日：2004-11-05
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/304 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

5. 发明申请

US20110095183A1 ELECTRON BEAM MEASUREMENT APPARATUS 有权
标题翻译：电子束测量装置
公开(公告)号：US20110095183A1
公开(公告)日：2011-04-28
申请号：US12982202
申请日：2010-12-30
申请人： Yasunari SOHDA , Shoji HOTTA , Shinji OKAZAKI , Muneyuki FUKUDA
发明人： Yasunari SOHDA , Shoji HOTTA , Shinji OKAZAKI , Muneyuki FUKUDA
IPC分类号： G01N23/00
CPC分类号： G03F7/7065 , G03F7/70541 , G03F7/70625 , G06T7/0006 , G06T2207/10056 , G06T2207/30148 , H01J2237/221 , H01J2237/24578 , H01J2237/2817 , H01L22/12
摘要： The present invention provides an electron beam measurement technique for measuring the shapes or sizes of portions of patterns on a sample, or detecting a defect or the like. An electron beam measurement apparatus has a unit for irradiating the patterns delineated on a substrate by a multi-exposure method, and classifying the patterns in an acquired image into multiple groups according to an exposure history record. The exposure history record is obtained based on brightness of the patterns and a difference between white bands of the patterns.
摘要翻译：本发明提供一种电子束测量技术，用于测量样品上图案的形状或尺寸，或检测缺陷等。电子束测量装置具有通过多曝光方法照射在基板上描绘的图案的单元，并且根据曝光历史记录将所获取的图像中的图案分类为多组。基于图案的亮度和图案的白色波段之间的差异获得曝光历史记录。

6. 发明申请

US20080006149A1 Compressor 审中-公开
标题翻译：压缩机
公开(公告)号：US20080006149A1
公开(公告)日：2008-01-10
申请号：US11824858
申请日：2007-07-03
申请人： Takayuki Kato , Fuminobu Enokijima , Masaki Inoue , Hajime Ikuno , Akira Yamada , Hiroshi Hohjo , Hiroshi Kawahara , Shoji Hotta , Isamu Ueda
发明人： Takayuki Kato , Fuminobu Enokijima , Masaki Inoue , Hajime Ikuno , Akira Yamada , Hiroshi Hohjo , Hiroshi Kawahara , Shoji Hotta , Isamu Ueda
IPC分类号： F02F7/00
CPC分类号： F04B39/12 , C22C21/02 , C22F1/043 , F04B27/1081 , F05C2201/021 , F05C2201/903
摘要： A compressor having a housing formed by a plurality of housing members that are connected together is disclosed. The compressor is configured in such a manner that refrigerant is compressed in the housing and discharged to the exterior. Each of the housing members contains 9 to 17 percent by mass of Si, 3.5 to 6 percent by mass of Cu, 0.2 to 1.2 percent by mass of Mg, 0.2 to 1.5 percent by mass of Fe, 0 to 1 percent by mass of Mn, 0.5 percent by mass or less of Ni, and a remaining portion containing Al and unavoidable impurities. It is preferred that the average hardness of each housing member is adjusted to HV130 to HV170 through solution heating in which the housing member is maintained at the treatment temperature of 450° C. to 510° C. for 0.5 hours or longer, followed by water quenching, and then by aging treatment in which the housing member is maintained at the treatment temperature of 170° C. to 230° C. for one to twenty-four hours after the c housing member is cast.
摘要翻译：公开了一种压缩机，其具有由连接在一起的多个壳体构件形成的壳体。压缩机构造成使得制冷剂在壳体中被压缩并排放到外部。每个壳体中含有9〜17质量％的Si，3.5〜6质量％的Cu，0.2〜1.2质量％的Mg，0.2〜1.5质量％的Fe，0〜1质量％的Mn ，0.5质量％以下的Ni，剩余部分含有Al和不可避免的杂质。优选地，通过溶液加热将每个壳体构件的平均硬度调节至HV130至HV170，其中壳体构件在450℃至510℃的处理温度下保持0.5小时或更长时间，然后是水淬火，然后通过老化处理，其中壳体构件被保持在处理温度为170℃至230℃，在c壳体构件被铸造之后一到二十四小时。

7. 发明申请

US20050090120A1 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20050090120A1
公开(公告)日：2005-04-28
申请号：US10967277
申请日：2004-10-19
申请人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
发明人： Norio Hasegawa , Katsuya Hayano , Shoji Hotta
IPC分类号： G03C5/00 , G03F1/30 , G03F1/32 , G03F1/68 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/311 , H01L21/768
CPC分类号： H01L21/76808 , G03F1/30 , G03F1/32 , G03F1/50 , H01L21/31144
摘要： In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.
摘要翻译：在掩模的多个转印区域的每一个的质量区域中，通过打开半色调膜形成多个透光图案。在每个透光图案中设置移相器，使得在通过相邻光传输图案传输的光之间发生180°的相位反转。在多个转印区域的稀疏区域中，通过打开半色调膜形成单独的透光图案。在透光图案之间的形状和尺寸都相同，所述光透射图案在转印区域之间的中心周围的质量和稀疏区域中对称地设置。配置区域中的移相器被布置成使得其中一个传送区域中的每个移相器的相位与其它传送区域中的相应部件的相位相反。在曝光处理中，这些传送区域在相同的芯片区域中彼此重叠。

8. 发明授权

US06555464B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06555464B2
公开(公告)日：2003-04-29
申请号：US10046814
申请日：2002-01-17
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

9. 发明申请

US20110155904A1 Method and Apparatus for Pattern Position and Overlay Measurement 有权
标题翻译：图形位置和叠加测量的方法和装置
公开(公告)号：US20110155904A1
公开(公告)日：2011-06-30
申请号：US12648766
申请日：2009-12-29
申请人： Shoji HOTTA , Norio Hasegawa
发明人： Shoji HOTTA , Norio Hasegawa
IPC分类号： G01N23/00 , G01B15/00
CPC分类号： G03F7/70466 , G03F7/70633 , G06T7/60 , G06T2207/10061 , G06T2207/30148 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.
摘要翻译：使用成像装置图案的系统和方法来测量半导体制造工艺中的不同层之间的覆盖层，例如双重图案化工艺。通过扫描电子显微镜获得图案特征的图像。使用图像中的图案化层的图案特征的位置来确定图案化层的位置。基于所确定的图案位置，以向量形式确定每个图案形成层相对于其它图案特征或图案化层的相对位置。叠加误差是根据相对位置与设计或模拟参考值的比较来确定的。可以通过利用图案对称性以高精度和精度测量覆盖层。

10. 发明授权

US07943903B2 Defect inspection method and its system 有权
标题翻译：缺陷检查方法及其系统
公开(公告)号：US07943903B2
公开(公告)日：2011-05-17
申请号：US12320574
申请日：2009-01-29
申请人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
发明人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： H01J37/153 , G01N23/00
CPC分类号： H01L22/12 , G06T7/0006 , G06T7/001 , G06T2207/10056 , G06T2207/30148 , H01L2924/0002 , H01L2924/00
摘要： A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
摘要翻译：一种能够容易地管理半导体集成图案的致命缺陷的方法，该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据，以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据分别。该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷，同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上，并将这些缺陷存储为热点信息。此外，该方法还能够将设计意图数据与热点信息组合，以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点，并显着缩短缺陷检查时间。

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