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1. 发明申请

WO2008062350A3 A SEALING STRUCTURE AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：一种密封结构和一种制造该结构的方法
公开(公告)号：WO2008062350A3
公开(公告)日：2008-07-17
申请号：PCT/IB2007054662
申请日：2007-11-15
申请人： NXP BV , DONKERS JOHANNES , HIJZEN ERWIN , MEUNIER-BEILLARD PHILIPPE , KOOPS GERHARD
发明人： DONKERS JOHANNES , HIJZEN ERWIN , MEUNIER-BEILLARD PHILIPPE , KOOPS GERHARD
IPC分类号： B81C1/00
CPC分类号： B81C1/00293 , B81B2201/0271 , B81C2203/0145
摘要： A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).
摘要翻译：一种制造结构（1100）的方法，该方法包括在衬底（101）上形成帽元件（401），去除帽元件（401）下面的衬底（101）的材料（103），从而形成间隙（401）和衬底（101）之间的衬底（802）以及重新布置帽元件（401）和/或衬底（101）的材料以由此合并帽元件（401）和衬底）以桥接间隙（802）。

2. 发明申请

WO2009130681A3 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：WO2009130681A3
公开(公告)日：2010-05-14
申请号：PCT/IB2009051672
申请日：2009-04-23
申请人： NXP BV , KOOPS GERHARD , MEUNIER-BEILLARD PHILIPPE
发明人： KOOPS GERHARD , MEUNIER-BEILLARD PHILIPPE
IPC分类号： B81C1/00
CPC分类号： B81C1/00333 , B81C2203/0136 , B81C2203/0145
摘要： A semiconductor device with a micro electro-mechanical system device is provided. The micro electro -mechanical system device comprises at least one cavity (19) over which a first layer (15, 17) is provided. The first layer (15) comprises a silicon layer (15) and at least one second layer (17) on top of the silicon layer (15) and at least one hole (16). The at least one second layer (17) constitutes a layer which prevents that silicon is epitaxially grown on it. The at least one hole (16) is closed by selective epitaxial silicon deposition on those parts of the silicon layer (15) which are not covered by the at least one outer layer (17).
摘要翻译：提供了具有微机电系统装置的半导体器件。微电子机械系统装置包括至少一个空腔（19），第一层（15,17）设置在该空腔上。第一层（15）包括在硅层（15）的顶部上的硅层（15）和至少一个第二层（17）和至少一个孔（16）。至少一个第二层（17）构成防止硅在其上外延生长的层。至少一个孔（16）通过选择性外延硅沉积封闭在硅层（15）的未被至少一个外层（17）覆盖的部分上。

3. 发明申请

WO2010023608A2 LOW COST MOS TRANSISTOR FOR RF APPLICATIONS 审中-公开
标题翻译：用于RF应用的低成本MOS晶体管
公开(公告)号：WO2010023608A2
公开(公告)日：2010-03-04
申请号：PCT/IB2009053707
申请日：2009-08-24
申请人： NXP BV , MEUNIER-BEILLARD PHILIPPE , HERINGA ANCO , DUFFY RAYMOND J
发明人： MEUNIER-BEILLARD PHILIPPE , HERINGA ANCO , DUFFY RAYMOND J
IPC分类号： H01L21/28
CPC分类号： H01L21/28114 , H01L21/26513 , H01L21/26586 , H01L21/2807 , H01L21/28247 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a MOS transistor for RF applications with a notched gate. The phrase "metal-oxide-semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal (usually aluminum in the very old days), current gate electrodes (including those up to the 65 nanometer technology node) are almost always made from a different material, polysilicon, but the terms MOS and CMOS nevertheless continue to be used for the modern descendants of the original process. Metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process.
摘要翻译：本发明涉及一种具有缺口门的RF应用的MOS晶体管。短语“金属氧化物半导体”是指一些场效应晶体管的物理结构，其中金属栅电极位于氧化物绝缘体的顶部，而金属栅电极又在半导体材料的顶部。代替金属（通常是在过去的铝），目前的栅极电极（包括直到65纳米技术节点的栅极）几乎总是由不同的材料，多晶硅制成，但是MOS和CMOS仍然继续用于现代后代的原始过程。随着CMOS工艺中高k介电材料的出现，金属门已经复出了。

4. 发明申请

WO2009031076A2 A TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：WO2009031076A2
公开(公告)日：2009-03-12
申请号：PCT/IB2008053448
申请日：2008-08-27
申请人： NXP BV , HERINGA ANCO , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND
发明人： HERINGA ANCO , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND
CPC分类号： H01L29/6656 , H01L21/2652 , H01L21/266 , H01L29/0847 , H01L29/6653 , H01L29/66598
摘要： A method of manufacturing a transistor (400), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), rearranging material of the spacer (201) so that the rearranged spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101) and an increased portion (302) of the substrate (102), and providing source/drain regions (402, 403) in a portion of the substrate (102) below the rearranged spacer (301).
摘要翻译：一种制造晶体管（400）的方法，该方法包括在衬底（102）上形成栅极（101），在栅极（101）的侧壁上和相邻部分（202）上形成间隔物（201）重新布置间隔件201的材料，使得重新布置的间隔件301仅覆盖栅极101的侧壁的下部303和栅极101的增加部分302，衬底（102）以及在重新布置的间隔物（301）下方的衬底（102）的一部分中提供源极/漏极区域（402,403）。

5. 发明申请

WO2009144619A3 MEMS DEVICES 审中-公开
标题翻译： MEMS器件
公开(公告)号：WO2009144619A3
公开(公告)日：2010-09-16
申请号：PCT/IB2009052086
申请日：2009-05-19
申请人： NXP BV , VERHEIJDEN GREJA J A M , MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M
发明人： VERHEIJDEN GREJA J A M , MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M
IPC分类号： B81C1/00
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： A method of manufacturing a MEMS device comprises forming a MEMS device element (14). A sacrificial layer (20) is provided over the device element and a package cover layer (22) is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening (22) in the cover layer and the at least one opening (24) is sealed by an anneal process.
摘要翻译：制造MEMS器件的方法包括形成MEMS器件元件（14）。牺牲层（20）设置在器件元件上方，并且封装覆盖层（22）设置在牺牲层上。使用覆盖层中的至少一个开口（22）去除牺牲层，并且通过退火工艺密封至少一个开口（24）。

6. 发明申请

WO2007036861A3 SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：具有双极晶体管的半导体器件及其制造方法
公开(公告)号：WO2007036861A3
公开(公告)日：2007-09-27
申请号：PCT/IB2006053446
申请日：2006-09-22
申请人： NXP BV , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND J , AGARWAL PRABHAT , HURKX GODEFRIDUS A M
发明人： MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND J , AGARWAL PRABHAT , HURKX GODEFRIDUS A M
IPC分类号： H01L29/737 , H01L21/331 , H01L29/08
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p- type doping profile (20) at or within the intermediate region (22) and thus excellent high- frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体本体的半导体器件（10），其包括具有发射极区（1），基极区（2）和集电极区（3）的双极晶体管，所述发射极区分别为N 通过提供合适的掺杂原子，P型导电性和P型导电性和N型导电性，其中基区（2）包括硅和锗的混合晶体，基极区（2）与发射极通过具有低于发射极区域（1）的掺杂浓度的掺杂浓度并且具有小于发射极区域（1）和发射极区域（1）的厚度的厚度的硅的中间区域（22）包括位于远离中间区域（22）的发射极区域（1）侧的硅和锗的混合晶体的子区域。根据本发明，包括硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1）直到与中间区域（22）交错，并且发射极区域（1）的掺杂原子是砷原子这种器件在中间区域（22）处或中间区域（22）内具有非常陡的n型掺杂分布（50）和非常陡的p型掺杂分布（20），因此具有高截止频率的优异的高频特性（FR）。优选地，发射极区域（1）在其上半部分掺杂有砷注入（I），最后的掺杂分布在RTA之后形成。本发明还包括一种制造根据本发明的装置（10）的方法。

7. 发明申请

WO2006109208A3 METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制备异相双极晶体管的方法
公开(公告)号：WO2006109208A3
公开(公告)日：2007-02-15
申请号：PCT/IB2006051005
申请日：2006-04-03
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M , HIJZEN ERWIN , MELAI JOOST
发明人： MEUNIER-BEILLARD PHILIPPE , DONKERS JOHANNES J T M , HIJZEN ERWIN , MELAI JOOST
IPC分类号： H01L21/331 , H01L29/16 , H01L29/423
CPC分类号： H01L29/66242 , H01L29/16 , H01L29/7378
摘要： The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting region (31) and an emitter region (29) are formed simultaneously and self-aligned to the base connecting region (23) without applying photolithographic techniques.
摘要翻译：本发明提供了一种用于制造具有基极连接区域（23）的异质结双极晶体管的方法，该基极连接区域（23）在不施加光刻技术的情况下与基极区域（7）自对准地形成。此外，在不使用光刻技术的情况下，集电极连接区域（31）和发射极区域（29）同时形成并且与基底连接区域（23）自对准。

8. 发明申请

WO2007000693A2 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2007000693A2
公开(公告)日：2007-01-04
申请号：PCT/IB2006052027
申请日：2006-06-22
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN NOORT WIBO D , SONSKY JAN , MEUNIER-BEILLARD PHILIPPE , HIJZEN ERWIN
发明人： VAN NOORT WIBO D , SONSKY JAN , MEUNIER-BEILLARD PHILIPPE , HIJZEN ERWIN
IPC分类号： H01L29/732 , H01L21/331 , H01L21/336 , H01L29/10 , H01L29/165 , H01L29/41 , H01L29/78
CPC分类号： H01L29/7378 , B82Y20/00 , H01L21/743 , H01L21/76229 , H01L21/8222 , H01L21/8249 , H01L29/1087 , H01L29/41708 , H01L29/42384 , H01L29/66242 , H01L29/78 , H01L29/78645 , H01L29/78696 , H01L31/035236 , H01L31/1812 , Y02E10/50
摘要： The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.
摘要翻译：本发明涉及一种具有衬底（11）和硅半导体本体（12）的半导体器件（10），其包括具有晶体管（T）的有源区（A）和围绕有源区的无源区（P）（A），并且设置有金属材料的埋入导电区域（1），所述埋入导电区域连接到从所述半导体主体（12）的表面凹陷的金属材料的导电区域（2），所述掩埋导电区域区域（1）在半导体本体（12）的表面处可电连接。根据本发明，在半导体本体（12）的有源区（A）的位置处形成掩埋导电区（1）。以这种方式，可以使用与周围的硅具有完全不同的晶体学特性的金属材料，在半导体本体（12）的有源区（A）中局部地产生非常低的掩埋电阻。这可以通过使用根据本发明的方法来实现。这种埋入的低电阻为双极晶体管和MOS晶体管提供了显着的优点。

9. 发明申请

WO2006109221A2 LATERAL BIPOLAR TRANSISTOR 审中-公开
标题翻译：横向双极晶体管
公开(公告)号：WO2006109221A2
公开(公告)日：2006-10-19
申请号：PCT/IB2006051045
申请日：2006-04-05
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUNIER-BEILLARD PHILIPPE , HUETING RAYMOND J E , DONKERS JOHANNES J T M , HIJZEN ERWIN
发明人： MEUNIER-BEILLARD PHILIPPE , HUETING RAYMOND J E , DONKERS JOHANNES J T M , HIJZEN ERWIN
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623 , H01L29/7378
摘要： The invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers (9, 10) and a removed gate electrode. An emitter region (41) and a collector region (45) are disposed in the source and drain regions, and a base region (43), comprising SiGe or p-type silicon, is provided adjacent to the emitter region (41) and the collector region (45). The base region (43) has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer (29) and an electrical contact (33) on the exposed area of the base region (43).
摘要翻译：本发明提供一种基于CMOS的横向双极晶体管及其制造方法。 CMOS器件形成了基于CMOS的横向双极晶体管的基础。 CMOS器件设置在硅，SOI或SSOI衬底上，并且包括源极和漏极区域，CMOS间隔物（9,10）和去除的栅电极。发射极区域（41）和集电极区域（45）设置在源极和漏极区域中，并且邻近发射极区域（41）设置包括SiGe或p型硅的基极区域（43），并且集电极区域（45）。基区（43）具有相对较大的暴露面积，因为其未被先前去除的栅电极覆盖。可以通过在基部区域（43）的暴露区域上设置金属层（29）和电触点（33）来减小基极电阻。

10. 发明申请

WO2006025035A3 VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SUCH DEVICES 审中-公开
标题翻译：垂直半导体器件及其制造方法
公开(公告)号：WO2006025035A3
公开(公告)日：2006-08-24
申请号：PCT/IB2005052873
申请日：2005-09-01
申请人： KONINKL PHILIPS ELECTRONICS NV , ROCHEFORT CHRISTELLE , HIJZEN ERWIN A , MEUNIER-BEILLARD PHILIPPE
发明人： ROCHEFORT CHRISTELLE , HIJZEN ERWIN A , MEUNIER-BEILLARD PHILIPPE
IPC分类号： H01L29/78 , H01L21/205 , H01L21/336 , H01L29/06
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/66712 , H01L29/7802
摘要： A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of trenches (20) in the drift region (12) and the opposite conductivity type material is epitaxially grown from the bottom of the trenches (20). The presence of the sidewall insulating material (31) prevents any defects in the charge compensation columns crossing into the drain drift material which therefore prevents any excessive leakage currents in the device (1). The insulating material (31) also prevents epitaxial growth on the trench sidewalls and hence substantially prevents forming voids in the trenches which would lessen the accuracy of charge compensation. The epitaxial growth by this method can be well controlled and may be stopped at an upper level (21) below the top major surface (10a). Thus, for example,20 trench-gates 22, 23 may be formed in the same trenches (20) above the compensation columns (30).
摘要翻译：垂直半导体器件，例如沟槽栅MOSFET功率晶体管（1）具有一个导电类型的漂移区域（12），其包含相反导电类型的间隔的垂直列（30），用于器件击穿电压的电荷补偿增加。绝缘材料（31）仅设置在漂移区域（12）中的沟槽（20）的侧壁上，并且相反的导电型材料从沟槽（20）的底部外延生长。侧壁绝缘材料（31）的存在防止了电荷补偿列中穿过漏极漂移材料的任何缺陷，从而防止了器件（1）中的任何过多的漏电流。绝缘材料（31）还防止沟槽侧壁上的外延生长，从而基本上防止在沟槽中形成空穴，这将降低电荷补偿的精度。通过该方法的外延生长可以很好地控制，并且可以在顶部主表面（10a）下方的上层（21）处停止。因此，例如，可以在补偿柱（30）上方的相同沟槽（20）中形成20个沟槽栅极22,23。

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