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1. 发明申请

WO2006109221A2 LATERAL BIPOLAR TRANSISTOR 审中-公开
标题翻译：横向双极晶体管
公开(公告)号：WO2006109221A2
公开(公告)日：2006-10-19
申请号：PCT/IB2006051045
申请日：2006-04-05
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUNIER-BEILLARD PHILIPPE , HUETING RAYMOND J E , DONKERS JOHANNES J T M , HIJZEN ERWIN
发明人： MEUNIER-BEILLARD PHILIPPE , HUETING RAYMOND J E , DONKERS JOHANNES J T M , HIJZEN ERWIN
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623 , H01L29/7378
摘要： The invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers (9, 10) and a removed gate electrode. An emitter region (41) and a collector region (45) are disposed in the source and drain regions, and a base region (43), comprising SiGe or p-type silicon, is provided adjacent to the emitter region (41) and the collector region (45). The base region (43) has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer (29) and an electrical contact (33) on the exposed area of the base region (43).
摘要翻译：本发明提供一种基于CMOS的横向双极晶体管及其制造方法。 CMOS器件形成了基于CMOS的横向双极晶体管的基础。 CMOS器件设置在硅，SOI或SSOI衬底上，并且包括源极和漏极区域，CMOS间隔物（9,10）和去除的栅电极。发射极区域（41）和集电极区域（45）设置在源极和漏极区域中，并且邻近发射极区域（41）设置包括SiGe或p型硅的基极区域（43），并且集电极区域（45）。基区（43）具有相对较大的暴露面积，因为其未被先前去除的栅电极覆盖。可以通过在基部区域（43）的暴露区域上设置金属层（29）和电触点（33）来减小基极电阻。

2. 发明申请

WO2005053033A3 TRENCH INSULATED GATE FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005053033A3
公开(公告)日：2006-03-09
申请号：PCT/IB2004052563
申请日：2004-11-26
申请人： KONINKL PHILIPS ELECTRONICS NV , HUETING RAYMOND J E , HIJZEN ERWIN A
发明人： HUETING RAYMOND J E , HIJZEN ERWIN A
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/36
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/42368 , H01L29/4238
摘要： The invention relates to a trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).
摘要翻译：本发明涉及一种具有漏极（8），漂移区（10）主体（12）和源极（14）的沟槽MOSFET。为了改善使用MOSFET作为控制和同步FET的品质因数，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在漂移中使用渐变掺杂分布区域（10）。

3. 发明申请

WO2004055882A8 METHOD OF MANUFACTURING A TRENCH-GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造三栅极半导体器件的方法
公开(公告)号：WO2004055882A8
公开(公告)日：2005-07-14
申请号：PCT/IB0306014
申请日：2003-12-08
申请人： KONINKL PHILIPS ELECTRONICS NV , HIJZEN ERWIN A , HUETING RAYMOND J E , IN T ZANDT MICHAEL A A
发明人： HIJZEN ERWIN A , HUETING RAYMOND J E , IN T ZANDT MICHAEL A A
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/518 , H01L29/7813
摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

4. 发明申请

WO2005053032A3 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005053032A3
公开(公告)日：2005-08-25
申请号：PCT/IB2004052562
申请日：2004-11-26
申请人： KONINKL PHILIPS ELECTRONICS NV , HUETING RAYMOND J E , HIJZEN ERWIN A
发明人： HUETING RAYMOND J E , HIJZEN ERWIN A
IPC分类号： H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/36 , H01L29/41
CPC分类号： H01L29/402 , H01L29/0696 , H01L29/0847 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4916 , H01L29/7813
摘要： The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the body region (12).
摘要翻译：本发明涉及一种具有漏极（8），漂移（10）主体（12）和源极（14）区域的沟槽MOSFET。漂移区被掺杂以具有高浓度梯度。邻近漂移区（10）设置的场板电极（34）和邻近体区（12）的栅电极（32）。

5. 发明申请

WO2005093841A3 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005093841A3
公开(公告)日：2006-05-18
申请号：PCT/IB2005051002
申请日：2005-03-23
申请人： KONINKL PHILIPS ELECTRONICS NV , HUETING RAYMOND J E
发明人： HUETING RAYMOND J E
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/423
CPC分类号： H01L29/7825 , H01L29/407 , H01L29/42376 , H01L29/7831
摘要： The invention relates to a trench MOSFET with a pair of source regions (12,22) on either side of trench (10). Body regions (14, 24) and drift regions (16,26) are provided under the source regions, connected together by drain region 8 extending under the trench. Field plate (30) is provided to control the drift region. The device can operate in a bidirectional manner controlling current passing in either direction between the source regions (12, 22).
摘要翻译：本发明涉及在沟槽（10）的任一侧上具有一对源区（12,22）的沟槽MOSFET。主体区域（14,24）和漂移区域（16,26）设置在源极区域下方，通过在沟槽下方延伸的漏极区域8连接在一起。提供场板（30）以控制漂移区域。该装置可以以双向方式操作，以控制在源极区域（12,22）之间沿任一方向通过的电流。

6. 发明申请

WO2005053031A3 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005053031A3
公开(公告)日：2005-08-25
申请号：PCT/IB2004052561
申请日：2004-11-26
申请人： KONINKL PHILIPS ELECTRONICS NV , HUETING RAYMOND J E
发明人： HUETING RAYMOND J E
IPC分类号： H01L29/06 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/41
CPC分类号： H01L29/1095 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/7827 , H01L29/7831
摘要： The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).
摘要翻译：本发明涉及一种具有漏极（8），子沟道区（10）主体（12）和源极（14）的沟槽MOSFET。子沟道区被掺杂成与主体（12）相同的导电类型，但掺杂密度较低。邻近子通道区域（10）10设置场板电极（34）和靠近主体（12）的栅电极（32）。

7. 发明申请

WO2004102670A3 SEMICONDUCTOR DEVICE WITH A FIELD SHAPING REGION 审中-公开
标题翻译：具有场形成区域的半导体器件
公开(公告)号：WO2004102670A3
公开(公告)日：2005-01-20
申请号：PCT/IB2004001527
申请日：2004-05-06
申请人： KONINKL PHILIPS ELECTRONICS NV , HERINGA ANCO , HUETING RAYMOND J E , SLOTBOOM JAN W
发明人： HERINGA ANCO , HUETING RAYMOND J E , SLOTBOOM JAN W
IPC分类号： H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/861 , H01L29/41
CPC分类号： H01L29/402 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/73 , H01L29/732 , H01L29/7802 , H01L29/7813 , H01L29/7824 , H01L29/861
摘要： A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.
摘要翻译：具有pn结（101）的半导体器件（例如二极管（200））具有与pn结相邻且可能桥接的绝缘材料场整形区域（201）。场成形区域（201）优选地具有高介电常数，并且经由电容性电压耦合区域（204,205）耦合到与施加到pn结的基本相同的电压。当在pn结（101）上施加反向电压并且器件不导通时，电容电场存在于场成形区域的一部分中，其延伸超过将存在的pn结耗尽区的极限在不存在场整形区域（201）的情况下，场成形区域中的电场引起限制到相应延伸的pn结耗尽区域（208,209）的拉伸电场和该器件的反向击穿电压的增加。

8. 发明申请

WO0169684A3 FIELD-EFFECT SEMICONDUCTOR DEVICES 审中-公开
标题翻译：场效应半导体器件
公开(公告)号：WO0169684A3
公开(公告)日：2002-01-03
申请号：PCT/EP0102271
申请日：2001-02-28
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： HUETING RAYMOND J E , HIJZEN ERWIN A , VAN DALEN ROB
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7813 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/7809 , H01L29/7811 , H01L29/7827 , H01L29/8122
摘要： A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.
摘要翻译：场效应半导体器件（例如沟槽栅型MOSFET）包括在半导体本体（10）的表面（10a）处的并排器件单元，以及至少一个漏极连接（41），其中，在漏极沟槽（40）中从主体表面（10a）延伸到下面的漏极区域（14a）。器件的通道容纳区域（15）横向延伸到漏极沟槽（40）。漏极沟槽（40）通过沟道容纳区域（15）的厚度延伸到下面的漏极区域（14a），并且漏极连接部分（41）通过中间绝缘体与沟道容纳区域（15）分离层（24）在排水沟槽（40）的侧壁上。可以实现紧凑的蜂窝布局，其中大部分的总细胞布局区域容纳传导通道（12）。分立器件中的配置避免了使用衬底传导路径的需要，因此有利地降低了器件的导通电阻。

9. 发明申请

WO0182359A3 METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A RECESSED INSULATING LAYER OF VARYING THICKNESS 审中-公开
标题翻译：制造具有变化厚度的被覆绝缘层的半导体器件的方法
公开(公告)号：WO0182359A3
公开(公告)日：2002-05-16
申请号：PCT/EP0104187
申请日：2001-04-12
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： HUETING RAYMOND J E , TIMMERLING CORNELIS E , MAAS HENRICUS G R
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/06 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/732 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/28
CPC分类号： H01L29/781 , H01L29/0649 , H01L29/0653 , H01L29/41708 , H01L29/41741 , H01L29/4175 , H01L29/42368 , H01L29/7813
摘要： In the manufacture of semiconductor devices that have an electrode (11) or a connection region (41) in an insulated trench (20), for example a trench-gate MOSFET on a bipolar transistor, process steps are performed to line the trench walls with a lower insulating layer (21) in a lower part of the trench and with a thicker upper insulating layer (22) in an upper part of the trench. The steps include: (a) etching the trench (20); (b) providing the lower insulating layer (21) on the trench walls; (c) depositing on the lower insulating layer (21) a further layer (51) of a different material; (d) depositing on the further layer (51) a filler material (52) that is of a different material from the further layer (51); (e) etching away the further layer (51) from the upper part of the trench walls while using the filler material (52) as an etchant mask, so as to form a space (50) adjacent to the upper part of the trench walls while leaving the further layer (51) in the lower part of the trench; and (f) providing the thicker upper insulating layer (22) in the space (50) adjacent to the upper part of the trench walls.
摘要翻译：在制造在绝缘沟槽（20）中具有电极（11）或连接区域（41）的半导体器件（例如双极型晶体管上的沟槽栅极MOSFET）中，执行工艺步骤以使沟槽壁与在沟槽的下部具有下绝缘层（21），并且在沟槽的上部具有较厚的上绝缘层（22）。步骤包括：（a）蚀刻沟槽（20）; （b）在沟槽壁上设置下绝缘层（21）; （c）在下绝缘层（21）上沉积不同材料的另一层（51）; （d）在所述另一层（51）上沉积与所述另一层（51）不同的材料的填充材料（52）; （e）在使用填充材料（52）作为蚀刻剂掩模的同时从沟槽壁的上部蚀刻掉另外的层（51），以形成邻近沟槽壁上部的空间（50）同时将另一层（51）留在沟槽的下部; 和（f）在与沟槽壁的上部相邻的空间（50）中设置较厚的上绝缘层（22）。

10. 发明申请

WO0157915A3 TRENCHED SCHOTTKY RECTIFIERS 审中-公开
标题翻译：带凹槽的肖特基整流器
公开(公告)号：WO0157915A3
公开(公告)日：2001-12-20
申请号：PCT/EP0100657
申请日：2001-01-22
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： HIJZEN ERWIN A , HUETING RAYMOND J E
IPC分类号： H01L29/40 , H01L29/47 , H01L29/872
CPC分类号： H01L29/407 , H01L29/872 , H01L29/8725
摘要： Inner trenches (11) of a trenched Schottky rectifier (1a; 1b; 1c; 1d) bound a plurality of rectifier areas (43a) where the Schottky electrode (3) forms a Schottky barrier 43 with a drift region (4). A perimeter trench (18) extends around the outer perimeter of the plurality of rectifier areas (43a). These trenches (11, 18) accommodate respective inner field-electrodes (31) and a perimeter field-electrode (38) that are connected to the Schottky electrode (3). The inner field-electrodes (11) are capacitively coupled to the drift region (4) via dielectric material (21) that lines the inner trenches (11). The perimeter field-electrode (38) is capacitively coupled across dielectric material (28) on the inside wall (18a) of the perimeter trench 18, without acting on any outside wall (18b). Furthermore, the inner and perimeter trenches (11, 18) are closely spaced and the intermediate areas (4a, 4b) of the drift region (4) are lowly doped. The spacing is so close and the doping is so low that the depletion layer (40) formed in the drift region (4), from the Schottky barrier (43) and from the field-relief regions (31,21; 38,28) in the blocking state of the rectifier, may deplete the whole of the intermediate areas (4a, 4b) between the trenches (11, 18) at a blocking voltage just below the breakdown voltage. This arrangement reduces the risk of premature breakdown that can occur at high field points in the depletion layer (40), especially at the perimeter of the array of rectifier areas (43a).
摘要翻译：沟槽式肖特基整流器（1a; 1b; 1c; 1d）的内部沟槽（11）界定了肖特基电极（3）与漂移区（4）形成肖特基势垒43的多个整流区域（43a）。周边沟槽（18）围绕多个整流器区域（43a）的外周边延伸。这些沟槽（11,18）容纳连接到肖特基电极（3）的相应的内部场电极（31）和周边场电极（38）。内部场电极（11）经由布置内部沟槽（11）的介电材料（21）电容耦合到漂移区（4）。周边场电极（38）在周边沟槽18的内壁（18a）上的电介质材料（28）上电容耦合，而不作用在任何外壁（18b）上。此外，内部和周边沟槽（11,18）紧密间隔并且漂移区（4）的中间区域（4a，4b）低度掺杂。该间隔非常接近并且掺杂非常低以至于形成在漂移区（4）中的肖特基势垒（43）和场抑制区（31,21; 38,28）中的耗尽层（40）在整流器的阻断状态下，可以在正好低于击穿电压的阻断电压下耗尽沟槽（11,18）之间的整个中间区域（4a，4b）。这种布置降低了在耗尽层（40）中的高场点处，特别是在整流器区域阵列（43a）的周边处可能发生的过早击穿的风险。

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