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1. 发明申请

WO2010023608A2 LOW COST MOS TRANSISTOR FOR RF APPLICATIONS 审中-公开
标题翻译：用于RF应用的低成本MOS晶体管
公开(公告)号：WO2010023608A2
公开(公告)日：2010-03-04
申请号：PCT/IB2009053707
申请日：2009-08-24
申请人： NXP BV , MEUNIER-BEILLARD PHILIPPE , HERINGA ANCO , DUFFY RAYMOND J
发明人： MEUNIER-BEILLARD PHILIPPE , HERINGA ANCO , DUFFY RAYMOND J
IPC分类号： H01L21/28
CPC分类号： H01L21/28114 , H01L21/26513 , H01L21/26586 , H01L21/2807 , H01L21/28247 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a MOS transistor for RF applications with a notched gate. The phrase "metal-oxide-semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal (usually aluminum in the very old days), current gate electrodes (including those up to the 65 nanometer technology node) are almost always made from a different material, polysilicon, but the terms MOS and CMOS nevertheless continue to be used for the modern descendants of the original process. Metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process.
摘要翻译：本发明涉及一种具有缺口门的RF应用的MOS晶体管。短语“金属氧化物半导体”是指一些场效应晶体管的物理结构，其中金属栅电极位于氧化物绝缘体的顶部，而金属栅电极又在半导体材料的顶部。代替金属（通常是在过去的铝），目前的栅极电极（包括直到65纳米技术节点的栅极）几乎总是由不同的材料，多晶硅制成，但是MOS和CMOS仍然继续用于现代后代的原始过程。随着CMOS工艺中高k介电材料的出现，金属门已经复出了。

2. 发明申请

WO2005062354A1 A SEMICONDUCTOR SUBSTRATE WITH SOLID PHASE EPITAXIAL REGROWTH WITH REDUCED JUNCTION LEAKAGE AND METHOD OF PRODUCING SAME 审中-公开
标题翻译：具有具有降低的接合泄漏的固相相位延迟的半导体基板及其制造方法
公开(公告)号：WO2005062354A1
公开(公告)日：2005-07-07
申请号：PCT/IB2004/052644
申请日：2004-12-02
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PAWLAK, Bartlomiej, J. , DUFFY, Raymond, J. , LINDSAY, Richard
发明人： PAWLAK, Bartlomiej, J. , DUFFY, Raymond, J. , LINDSAY, Richard
IPC分类号： H01L21/265
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/2022 , H01L21/26506 , H01L21/2652 , H01L29/6659 , H01L29/7833
摘要： Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f)applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant.
摘要翻译：一种制造半导体器件的方法，包括：a）提供半导体衬底，b）通过合适的注入在所述半导体衬底的顶层中制造第一非晶层，所述第一非晶层具有第一深度，c）掺杂剂进入半导体衬底以提供具有第一掺杂分布的第一非晶层，d）施加第一固相外延再生长作用以部分地重新生长第一非晶层并形成具有小于第一非晶层的第二深度的第二非晶层深度并激活第一掺杂剂，e）将第二掺杂剂注入到半导体衬底中以向第二非晶层提供具有比第一掺杂分布更高的掺杂浓度的第二掺杂分布，f）施加第二固相外延再生作用再生第二非晶层并激活第二掺杂剂。

3. 发明申请

WO2009031076A2 A TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：WO2009031076A2
公开(公告)日：2009-03-12
申请号：PCT/IB2008053448
申请日：2008-08-27
申请人： NXP BV , HERINGA ANCO , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND
发明人： HERINGA ANCO , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND
CPC分类号： H01L29/6656 , H01L21/2652 , H01L21/266 , H01L29/0847 , H01L29/6653 , H01L29/66598
摘要： A method of manufacturing a transistor (400), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), rearranging material of the spacer (201) so that the rearranged spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101) and an increased portion (302) of the substrate (102), and providing source/drain regions (402, 403) in a portion of the substrate (102) below the rearranged spacer (301).
摘要翻译：一种制造晶体管（400）的方法，该方法包括在衬底（102）上形成栅极（101），在栅极（101）的侧壁上和相邻部分（202）上形成间隔物（201）重新布置间隔件201的材料，使得重新布置的间隔件301仅覆盖栅极101的侧壁的下部303和栅极101的增加部分302，衬底（102）以及在重新布置的间隔物（301）下方的衬底（102）的一部分中提供源极/漏极区域（402,403）。

4. 发明申请

WO2006033086A2 METHOD OF MAKING SHALLOW SEMICONDUCTOR JUNCTIONS 审中-公开
标题翻译：制作浅的半导体结的方法
公开(公告)号：WO2006033086A2
公开(公告)日：2006-03-30
申请号：PCT/IB2005/053157
申请日：2005-09-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DUFFY, Raymond, J.
发明人： DUFFY, Raymond, J.
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/324
摘要： Phosphorous ions 6 are implanted into a first major surface 4 of a silicon body 2 to render the first major surface amorphous. Then the silicon body is annealed at a temperature of not greater than 800°C. It has been discovered that the phosphorous 6 diffuses towards the first major surface 4 making the junction shallower.
摘要翻译：将磷离子6注入到硅本体2的第一主表面4中以使第一主表面非晶化。然后硅体在不高于800℃的温度下退火。已经发现，磷6向第一主表面4扩散，使结更浅。

5. 发明申请

WO2010023608A3 LOW COST MOS TRANSISTOR FOR RF APPLICATIONS 审中-公开
公开(公告)号：WO2010023608A3
公开(公告)日：2010-03-04
申请号：PCT/IB2009/053707
申请日：2009-08-24
申请人： NXP B.V. , MEUNIER-BEILLARD, Philippe , HERINGA, Anco , DUFFY, Raymond, J.
发明人： MEUNIER-BEILLARD, Philippe , HERINGA, Anco , DUFFY, Raymond, J.
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/265
摘要： The present invention relates to a MOS transistor for RF applications with a notched gate. In summary, the present invention creates a lowly doped drain extention by enhanced diffusion due to high dose implants. The resulting higher overlap capacitance between the extention and the gate is remedied by making in this overlap area the distance between gate and extention larger by removal of part of the gate in the overlap area. The resulting transistor features a relatively high breakdown voltage, a relatively short channel length and a relatively low gate capacitance. This allows high frequency operation in combination with high operating voltages. The novelty is the combination in the processing of a method to process a notched gate and the usage of enhanced high concentration diffusion.

6. 发明申请

WO2009031076A3 A TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2009031076A3
公开(公告)日：2009-03-12
申请号：PCT/IB2008/053448
申请日：2008-08-27
申请人： NXP B.V. , HERINGA, Anco , MEUNIER-BEILLARD, Philippe , DUFFY, Raymond
发明人： HERINGA, Anco , MEUNIER-BEILLARD, Philippe , DUFFY, Raymond
IPC分类号： H01L21/266 , H01L21/336 , H01L21/265 , H01L29/08
摘要： A method of manufacturing a transistor (400), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), rearranging material of the spacer (201) so that the rearranged spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101) and an increased portion (302) of the substrate (102), and providing source/drain regions (402, 403) in a portion of the substrate (102) below the rearranged spacer (301).

7. 发明申请

WO2007036861A3 SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：具有双极晶体管的半导体器件及其制造方法
公开(公告)号：WO2007036861A3
公开(公告)日：2007-09-27
申请号：PCT/IB2006053446
申请日：2006-09-22
申请人： NXP BV , MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND J , AGARWAL PRABHAT , HURKX GODEFRIDUS A M
发明人： MEUNIER-BEILLARD PHILIPPE , DUFFY RAYMOND J , AGARWAL PRABHAT , HURKX GODEFRIDUS A M
IPC分类号： H01L29/737 , H01L21/331 , H01L29/08
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p- type doping profile (20) at or within the intermediate region (22) and thus excellent high- frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体本体的半导体器件（10），其包括具有发射极区（1），基极区（2）和集电极区（3）的双极晶体管，所述发射极区分别为N 通过提供合适的掺杂原子，P型导电性和P型导电性和N型导电性，其中基区（2）包括硅和锗的混合晶体，基极区（2）与发射极通过具有低于发射极区域（1）的掺杂浓度的掺杂浓度并且具有小于发射极区域（1）和发射极区域（1）的厚度的厚度的硅的中间区域（22）包括位于远离中间区域（22）的发射极区域（1）侧的硅和锗的混合晶体的子区域。根据本发明，包括硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1）直到与中间区域（22）交错，并且发射极区域（1）的掺杂原子是砷原子这种器件在中间区域（22）处或中间区域（22）内具有非常陡的n型掺杂分布（50）和非常陡的p型掺杂分布（20），因此具有高截止频率的优异的高频特性（FR）。优选地，发射极区域（1）在其上半部分掺杂有砷注入（I），最后的掺杂分布在RTA之后形成。本发明还包括一种制造根据本发明的装置（10）的方法。

8. 发明申请

WO2005062353A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2005062353A1
公开(公告)日：2005-07-07
申请号：PCT/IB2004/052578
申请日：2004-11-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PAWLAK, Bartlomiej, J. , DUFFY, Raymond, J.
发明人： PAWLAK, Bartlomiej, J. , DUFFY, Raymond, J.
IPC分类号： H01L21/265
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L29/1083 , H01L29/6653
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of silicon is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type, which both are provided with extensions (2A,3A) and with a channel region (4) of a second conductivity type, opposite to the first conductivity type, between the source region (2) and the drain region (3) and with a gate region (5) separated from the surface of the semiconductor body (1) by a gate dielectric (6) above the channel region (4), and wherein a pocket region (7) of the second conductivity type and with a doping concentration higher than the doping concentration of the channel region (4) is formed below the extensions (2A,3A), and wherein the pocket region (7) is formed by implanting heavy ions in the semiconductor body (1), after which implantation a first annealing process is done at a moderate temperature and a second annealing process with fast ramp-up is done at a higher temperature. According to the invention, the method is characterized in that between the two annealing processes amorphous silicon in the semiconductor body (1) is intentionally kept present in a surface region of the semiconductor body (1) which extends from the surface of the semiconductor body up to about the projected range of the implanted pocket region (7). This may be obtained by e.g. timely interrupting the first annealing process or by making the relevant region amorphous by an implantation of inert ions between the first and the second annealing process. In this way a very abrupt and narrow doping profile in the pocket region (7) is obtained, which is advantageous for future CMOS devices.
摘要翻译：本发明涉及一种制造具有场效应晶体管的半导体器件（10）的方法，其中在其表面上设置有源区（2）和漏区（3）的硅半导体本体（1）），其在源极区域（2）和漏极区域（2）之间设置有延伸部（2A，3A）和与第一导电类型相反的第二导电类型的沟道区域（4）（3）并且具有通过沟道区域（4）上方的栅极电介质（6）与半导体本体（1）的表面分离的栅极区域（5），并且其中第二导电类型的袋区域（7）并且在延伸部（2A，3A）的下方形成掺杂浓度高于沟道区域（4）的掺杂浓度的掺杂浓度，并且其中通过在半导体本体（1）中注入重离子形成袋区域（7）之后，在适度的温度下进行第一次退火处理 e和在较高温度下进行快速升温的第二退火工艺。根据本发明，该方法的特征在于，在两个退火处理之间，半导体本体（1）中的非晶硅有意地保持在半导体本体（1）的从半导体本体的表面向上延伸的表面区域中到约植入袋区域（7）的投影范围。这可以通过例如及时中断第一退火工艺，或者通过在第一和第二退火工艺之间注入惰性离子使相关区域变为无定形。以这种方式，获得了在口袋区域（7）中非常突然和窄的掺杂分布，这对将来的CMOS器件是有利的。

9. 发明申请

WO2007036861A2 SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：具有双极晶体管的半导体器件及制造这种器件的方法
公开(公告)号：WO2007036861A2
公开(公告)日：2007-04-05
申请号：PCT/IB2006/053446
申请日：2006-09-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , DUFFY, Raymond, J. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
发明人： MEUNIER-BEILLARD, Philippe , DUFFY, Raymond, J. , AGARWAL, Prabhat , HURKX, Godefridus, A., M.
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p- type doping profile (20) at or within the intermediate region (22) and thus excellent high- frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体主体的半导体器件（10），该半导体主体包括具有发射极区（1），基极区（2）和集电极区（ 3），其通过提供合适的掺杂原子分别具有N型导电性，P型导电性和N型导电性，其中基极区（2）包括硅和锗的混合晶体，基极区（2）通过掺杂浓度低于发射极区域（1）的掺杂浓度并且厚度小于发射极区域（1）的厚度的中间区域（22）与发射极区域分开）并且发射极区（1）包括包含位于发射极区（1）的远离中间区（22）侧的硅和锗的混合晶体的子区。根据本发明，包含硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1），直到与中间区域（22）交织并且发射极区域（1）的掺杂原子是砷原子。这种器件在中间区域（22）处或内部具有非常陡峭的n型掺杂分布（50）和非常陡峭的p型掺杂分布（20），因此具有高截止频率（FR）。优选地，发射极区（1）在其上半部分掺杂有砷注入（I），最终的掺杂分布在RTA之后形成。本发明还包括制造根据本发明的装置（10）的方法。

10. 发明申请

WO2006033086A3 METHOD OF MAKING SHALLOW SEMICONDUCTOR JUNCTIONS 审中-公开
标题翻译：制造薄膜半导体结的方法
公开(公告)号：WO2006033086A3
公开(公告)日：2006-09-08
申请号：PCT/IB2005053157
申请日：2005-09-23
申请人： KONINKL PHILIPS ELECTRONICS NV , DUFFY RAYMOND J
发明人： DUFFY RAYMOND J
IPC分类号： H01L21/265 , H01L21/324 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/324
摘要： Phosphorous ions 6 are implanted into a first major surface 4 of a silicon body 2 to render the first major surface amorphous. Then the silicon body is annealed at a temperature of not greater than 800°C. It has been discovered that the phosphorous 6 diffuses towards the first major surface 4 making the junction shallower.
摘要翻译：将磷离子6注入到硅体2的第一主表面4中，以使第一主表面无定形。然后，硅体在不大于800℃的温度下退火。已经发现，磷6向第一主表面4扩散，从而使结更浅。

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