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1. 发明专利

JPH01295463A THIN FILM SEMICONDUCTOR ELEMENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01295463A
公开(公告)日：1989-11-29
申请号：JP12632388
申请日：1988-05-24
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： MURAMOTO HIDETOSHI , SAKAKIBARA NOBUYOSHI , FUJINO SEIJI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L29/78 , H01L21/20 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
摘要： PURPOSE:To improve step coverage property, by covering a semiconductor island having a right-angle edge part with a dummy insulating film having a smoothly curved surface. CONSTITUTION:A semiconductor film 10 which is formed on an insulating substrate 1 is divided by anisotropic etching to form a plurality of semiconductor islands 2. A dummy insulating film 3 having a smoothly curved surface is formed so as to cover at least a plurality of the semiconductor islands 2. Of the dummy insulating film 3, a part covering a functional-element forming surface 2a on the upper surface of each semiconductor island is removed by isotropic etching. Thereafter, a film layer 4 constituting functional elements is overlapped and formed on the upper part. Even if the film layers are overlapped and formed on the exposed element-forming surface 2a and dummy insulating film 3, there is no problem such as the local thinning of the film layers, and the step coverage property is improved.

2. 发明专利

JPH01289109A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01289109A
公开(公告)日：1989-11-21
申请号：JP11895388
申请日：1988-05-16
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： KATADA MITSUTAKA , FUJINO SEIJI , MURAMOTO HIDETOSHI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L21/20
摘要： PURPOSE:To display excellent interfacial characteristics subject to less transition and defects by a method wherein, after forming an amorphous layer on the mirror surface part of a semiconductor substrate, two substrates are bonded together through the intermediary of the amorphous layer to solid-deposit the amorphous layer. CONSTITUTION:The ground surface of a mirror-ground low concentration N substrate 20 is implanted with Si ion to form an amorphous layer 21 by making the crystal surface amorphous. Both of the substrate 20 and another mirror- ground high concentration N substrate 22 are subjected to the surface cleaning process a and hydrophilic process (b). First, the formation surface of a layer 21 on the substrate 20 is brought into contact with the mirror-ground surface of the substrate 22 to form a contact substrate for heat treatment (exceeding 600 deg.C). Through these procedures, the solid epitaxial deposition is performed conforming to the crystalline structure of the substrate 22 to form a boundary layer 30. Secondly, the layer 20 is lapped or mirror-ground down to proper thickness to form a junction substrate 23. Finally, a high concentration P layer 27 is formed and then electrodes 28, 29 are formed to form a diode 24 in high breakdown strength.

3. 发明专利

JPH02178965A INSULATED ISOLATION TYPE FIELD-EFFECT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02178965A
公开(公告)日：1990-07-11
申请号：JP33164488
申请日：1988-12-29
申请人： NIPPON DENSO CO , NIPPON SOKEN
发明人： SAKAKIBARA NOBUYOSHI , FUJINO SEIJI , MURAMOTO HIDETOSHI , HATTORI TADASHI , YAMAOKA MASAMI
IPC分类号： H01L27/00 , H01L27/10 , H01L27/12 , H01L29/786
摘要： PURPOSE:To stabilize the electrical characteristics of an SOI element, and to prevent a back channel by applying bias voltage to a conductor electrically conducted with a channel region and electrically isolated from source-drain regions. CONSTITUTION:A conductor 21, which is arranged just under a channel region 33 while being formed onto at least an insulator 20 and buried into the insulator 20, a top face of which in integral combination is formed to a plane shape and which is conducted electrically with the channel region 33 and isolated electrically from source-drain regions 32a, 32b, is shaped. Consequently, the conductor 21 is formed just under the channel region 33 while being electrically conducted with the channel region 33, thus applying bias voltage to the conductor 21 even when any potential is applied to a semiconductor substrate 10. Accordingly, the electrical characteristics of an SOI(Silicon on Insulator) element are stabilized, and the generation of a back channel can be prevented.

4. 发明专利

JPH0243771A MANUFACTURE OF INSULATED GATE TYPE SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH0243771A
公开(公告)日：1990-02-14
申请号：JP19492988
申请日：1988-08-04
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： FUJINO SEIJI , SAKAKIBARA NOBUYOSHI , MURAMOTO HIDETOSHI , HATTORI TADASHI , MUTO KOJI
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78 , H01L29/786
摘要： PURPOSE:Not only to alleviate the ruggedness of a polycrystalline silicon surface, which is made to serve as an active region, so as to eliminate a gate failure due to a short circuit but also to improve a semiconductor element in electrical properties such as a carrier mobility and the like by a method wherein a polycrystalline silicon film is formed in film as thick as a specified value or more, which is covered with a cap layer and subjected to a heat treatment at a high temperature and whose surface is flattened. CONSTITUTION:In the manufacture of an insulated gate type semiconductor element provided with a polycrystalline silicon layer 3, serving as an active region deposited on an insulating layer 2, deposited on an insulating layer 2, the polycrystalline silicon layer 3 is formed in film as thick as more than 0.5mum. Then, after the surface of the polycrystalline silicon layer 3 is flattened, the vicinity of the flattened surface of the silicon layer 3, which is thicker than 0.5mum, is made to serve as a channel region 3b-2, and a gate electrode 5 is formed on the region 3b-2 through the intermediary of a gate insulating film 4 and concurrently a drain region 3b-1 and a source region 3b-2 are formed inside the polycrystalline silicon layer 3 so as to be connected to the channel region 3b-2.

5. 发明专利

JPH0322567A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0322567A
公开(公告)日：1991-01-30
申请号：JP15798889
申请日：1989-06-20
申请人： NIPPON SOKEN , NIPPON DENSO CO
发明人： MURAMOTO HIDETOSHI , FUJINO SEIJI , SAKAKIBARA NOBUYOSHI , HATTORI TADASHI , SAKAKIBARA TOSHIO
IPC分类号： H01L27/12 , H01L29/78 , H01L29/786
摘要： PURPOSE:To enhance an insulating film in step coverage and dielectric breakdown strength by a method wherein the upper end of the peripheral part of a silicon island is formed into a shape with a curved surface whose curvature is so prescribed to enable the silicon island to be gradually thin. CONSTITUTION:A polycrystalline Si film 10 is formed on an insulating substrate I where a field insulating film 12 has been laid, a resist R1 is formed only on a part where a silicon island is to be formed, which is patterned, and then the resist R1 is removed. The whole face of the substrate 1 on which the silicon island 2 has been formed is subjected to a dry oxidation process at a temperature of 1200 deg.C or so for 6 hours or so to form an insulating film 23 of SiO2, and then the insulating film 23 is etched to remove. By this process, the upper peripheral part of the silicon island 2 is formed into a smoothly curved surface. Then, spin-on-glass is applied thereon to form a dummy oxide film 3, which is etched and then subjected to a dry etching to form a gate insulating film 4.

6. 发明专利

JPH08274309A MANUFACTURE OF MIS TRANSISTOR 失效
公开(公告)号：JPH08274309A
公开(公告)日：1996-10-18
申请号：JP7192495
申请日：1995-03-29
申请人： NIPPON DENSO CO
发明人： KATADA MITSUTAKA , ISOBE YOSHIHIKO , MURAMOTO HIDETOSHI
IPC分类号： H01L21/336 , H01L21/265 , H01L29/78
摘要： PURPOSE: To obtain a stable transistor characteristic by lessening the dispersion of the suppression of a short channel effect. CONSTITUTION: (a) A gate electrode 13 is formed on a silicon substrate 11 with a gate insulating film 12 between. (b) Oxide films 14a, 14b are formed on the surfaces of the gate electrode 13 and the silicon substrate 11. (c) With the insulating film 14a formed on the side surface of the gate electrode 13 used as a reference, phosphor ions 15 or ions 15 of a compound containing phosphor are implanted from an oblique direction, and punch-through suppression layers 16a, 6b are formed in the silicon substrate 11. (d) Besides, BF2 ions 18 are implanted to the surface of a silicon substrate 11 from the vertical direction using the gate electrode 13 and the insulating film 14a formed on its side surfaces as a mask. (e) A source and a drain 18a and 18b are formed by activating these BF2 ions implanted.

7. 发明专利

JPH0774351A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0774351A
公开(公告)日：1995-03-17
申请号：JP21757993
申请日：1993-09-01
申请人： NIPPON DENSO CO
发明人： MURAMOTO HIDETOSHI , ONODA KUNIHIRO
IPC分类号： H01L29/78
摘要： PURPOSE:To enable a semiconductor device provided with at least a circuit which contains an analog signal processing system to be lessened in noises without increasing it in chip area. CONSTITUTION:An N-type buried layer 12 is formed on a part of the surface of a P-type semiconductor substrate 11 where a gate electrode 14, and a drain 15 and a source 16 are formed on both the sides of the N-type buried layer 12. The drain 15 is composed of a first drain impurity layer 151 and a second drain impurity layer 152 which overlap each other, wherein the impurity layers 151 and 152 are isolated from each other by a P-type insulating layer 171. The source 16 is also composed of a first source impurity layer 161 and a second source impurity layer 162 which overlap each other, wherein the impurity layers 161 and 162 are isolated from each other by a P-type insulating layer 172. The tip of the second drain impurity region 152 is made to extend under a gate electrode 14, and the first drain impurity region 151 is set in potential so as to set a potential difference from the source smaller than that between any other regions and the source.

8. 发明专利

JPH06196708A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06196708A
公开(公告)日：1994-07-15
申请号：JP34470492
申请日：1992-12-24
申请人： NIPPON DENSO CO
发明人： OYA NOBUYUKI , MURAMOTO HIDETOSHI , OOHARA ATSUSHI , FUKATSU SHIGEMITSU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide a nonvolatile semiconductor memory device such as EPROM in which the current capacity of elements is improved and flush EEPROM. CONSTITUTION:An LOCOS oxide film 12 is so formed in the surface of a silicon semiconductor substrate 11 as to surround the region of elements and at the same time a floating gate 14 is formed in the surface of the substrate 11 through a gate oxide film 13, and further a control gate 16 is formed through an insulating films 15. A channel stop region 17 is so formed as to correspond to the outer circumference of the floating gate 14, and also a region 18 is so formed under the floating gate 14 and also under a part of the LOCOS oxide film 12 or under a birds peak part 121 so as to have lower concentration than that directly under the gate oxide film. When voltage is applied to the control gate, a channel is formed in the region of low concentration, so that since the width of the gates of elements is virtually widened, current capacity is increased without changing the area of a cell.

9. 发明专利

JPH0368170A MANUFACTURE OF THIN FILM SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH0368170A
公开(公告)日：1991-03-25
申请号：JP20415789
申请日：1989-08-07
申请人： NIPPON SOKEN
发明人： MURAMOTO HIDETOSHI , HIRAYAMA TSUKASA , FUJINO SEIJI
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76 , H01L27/12 , H01L29/786
摘要： PURPOSE:To prevent a thin film semiconductor element from decreasing in dielectric breakdown strength and to improve it in degree of integration by a method wherein the side faces of two or more semiconductor islands are completely covered with a side face insulating film, the upsides of the islands are exposed, and a film layer constituting a functional element is formed overlapping the exposed part concerned. CONSTITUTION:A polycrystalline Si layer 20 is formed on an insulating substrate 11, and a protective oxide film 8 and a silicon nitride film 9 are formed thereon. Then, a resist 100 is formed only on a semiconductor island forming part, which is patterned. After the resist 100 is removed, the silicon nitride film 9 patterned at the same time with a semiconductor island 2 is selectively oxidized to form a side face insulating film 3. Next, an upside 2a of the semiconductor island 2 is exposed through selective etching. Then, impurity is diffused into the semiconductor island 2 to form a p -type and an N -type region. In succession, a gate insulating film 4 is uniformly formed. Then, a polycrystalline Si gate 5 is formed at a prescribed position on the upsides of the gate insulating film 4 and the side face insulating film 3.

10. 发明专利

JPH03153080A MANUFACTURE OF SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH03153080A
公开(公告)日：1991-07-01
申请号：JP29318289
申请日：1989-11-10
申请人： NIPPON SOKEN
发明人： HIRAYAMA TSUKASA , MURAMOTO HIDETOSHI , FUJINO SEIJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
摘要： PURPOSE:To make a gate insulating film uniform by coating an insulating film with a polycrystalline silicon film, and forming an oxidation preliminary layer uniform in oxidation speed on an element formation face, subsequently constituting a gate on a silicon film through a gate insulating film with the oxidation preliminary layer as a gate insulating film. CONSTITUTION:A polycrystalline Si film 3 is made on an insulating substrate where a field insulating film 2 is formed by dry-oxidating the surface of an Si single crystalline layer 1, and their grains are made large by annealing. And a resist is made only at the part to form a silicon island and is masked, and after the patterning by anisotropic etching the resist is removed. Oxigen ion implantation is done to the whole face of the insulating substrate where a silicon island 3 is formed, and the SixOy layer 4a as an oxidation preliminary layer is made near the surface of the silicon island 3, but subsequently it is heated in oxygen atmosphere to form a gate insulating film 4. Hereupon, since the SixOy layer is in amorphous condition where the crystals of silicon is disordered by the oxygen ion implantation, a gate insulating film 4 uniform in thickness can be made.

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