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1. 发明专利

FR2720856B1 未知
公开(公告)号：FR2720856B1
公开(公告)日：1998-04-17
申请号：FR9505122
申请日：1995-04-28
申请人： NIPPON DENSO CO
发明人： YAMAOKA TOORU , KOMURA ATSUSHI , YAMAUCHI TAKESHI , ISOBE YOSHIHIKO , YAMANE HIROYUKI
IPC分类号： H01L21/285 , H01L21/768 , H01L29/45 , H01L23/532
摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 mum, the number of Al voids with widths of over 0.3 mum is practically reduced to 0.

2. 发明专利

DE4442067A1 Programmable permanent memory cell 未知
公开(公告)号：DE4442067A1
公开(公告)日：1995-06-01
申请号：DE4442067
申请日：1994-11-25
申请人： NIPPON DENSO CO
发明人： IIDA MAKIO , FUJII TETSUO , ISOBE YOSHIHIKO
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
摘要： The permanent memory cell includes a MOS transistor with a gate electrode (51) formed on a surface of a semiconductor substrate (1). A floating electrode (F) contains the gate electrode and a capacitance electrode section (50) formed by extension of the gate electrode. A control electrode (A) is composed of a semiconductor region of a conductivity type which is arranged directly below the capacitance electrode section. an isolation layer is arranged between the two. An isolator surrounds a side and the base of the semiconductor regin which forms the control electrode.

3. 发明专利

DE69108957D1 未知
公开(公告)号：DE69108957D1
公开(公告)日：1995-05-24
申请号：DE69108957
申请日：1991-02-21
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , IIDA MAKIO , MIURA SHOJI , KAJIURA KEIZOU , SUZUKI MIKIMASA , SAITO MASAMI
IPC分类号： H01L27/04 , H01L21/02 , H01L21/82 , H01L21/822 , H01L21/3205 , H01L23/525

4. 发明专利

DE19521985A1 Semiconductor device with fuse(s) 未知
公开(公告)号：DE19521985A1
公开(公告)日：1996-01-04
申请号：DE19521985
申请日：1995-06-16
申请人： NIPPON DENSO CO
发明人： YAMADERA HIDEYA , OHWAKI TAKESHI , TAGA YASUNORI , IIDA MAKIO , OHKAWA MAKOTO , ABE HIROFUMI , ISOBE YOSHIHIKO
IPC分类号： H01L23/525 , H01L27/112 , H01L21/8246
摘要： The device includes a silicon substrate (1), an insulating layer (2), and a thin layer resistance (3). The insulation layer is of silicon oxide and is formed on the substrate. The thin resistance layer acts as a melting fuse layer and is of chrome, silicon, and tungsten. A blocking metal layer (4), a wiring part (5) of aluminium or some alloy both formed on the thin layer. A passivating layer (8) is in contact with the wiring and the thin layer and is composed of silicon nitride, and an insulating material containing silicon. The blocking layer is made of tungsten or a tungsten alloy.

5. 发明专利

FR2720856A1 未知
公开(公告)号：FR2720856A1
公开(公告)日：1995-12-08
申请号：FR9505122
申请日：1995-04-28
申请人： NIPPON DENSO CO
发明人： YAMAOKA TOORU , KOMURA ATSUSHI , YAMAUCHI TAKESHI , ISOBE YOSHIHIKO , YAMANE HIROYUKI
IPC分类号： H01L21/285 , H01L21/768 , H01L29/45 , H01L23/532
摘要： The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 mum, the number of Al voids with widths of over 0.3 mum is practically reduced to 0.

6. 发明专利

DE69108957T2 未知
公开(公告)号：DE69108957T2
公开(公告)日：1995-11-16
申请号：DE69108957
申请日：1991-02-21
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , IIDA MAKIO , MIURA SHOJI , KAJIURA KEIZOU , SUZUKI MIKIMASA , SAITO MASAMI
IPC分类号： H01L27/04 , H01L21/02 , H01L21/82 , H01L21/822 , H01L21/3205 , H01L23/525

7. 发明专利

DE19515564A1 Electrode with semiconductor substrate for semiconductor component 未知
公开(公告)号：DE19515564A1
公开(公告)日：1995-11-02
申请号：DE19515564
申请日：1995-04-27
申请人： NIPPON DENSO CO
发明人： YAMAOKA TOORU , KOMURA ATSUSHI , YAMAUCHI TAKESHI , ISOBE YOSHIHIKO , YAMANE HIROYUKI
IPC分类号： H01L21/285 , H01L21/768 , H01L29/45 , H01L29/40 , H01L21/283
摘要： The electrode includes a semiconductor substrate (10), an insulating intermediate film (11), and a titanium nitride barrier layer (13). The intermediate film is formed on the substrate and has a contact hole (17). The barrier layer is formed on the intermediate film such that it contacts the semiconductor substrate through the contact hole via a titanium layer (12) and a titanium silicide layer (16).On the barrier layer is formed an Al alloy wiring layer (15) and a distortion relief layer (14) with a thickness of at least 10 microns. The relief layer is made of an intermetal compound contg. Al and Ti and it is located on a boundary face between the barrier layer and the wiring layer.

8. 发明专利

JPH08316423A OXIDE FILM FORMING METHOD OF POLYSILICON SEMICONDUCTOR LAYER 失效
公开(公告)号：JPH08316423A
公开(公告)日：1996-11-29
申请号：JP14544895
申请日：1995-05-18
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , TAI AKIRA
IPC分类号： H01L27/04 , H01L21/316 , H01L21/318 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088
摘要： PURPOSE: To enable independent control of each oxide film thickness, when oxide films are simultaneously formed on the parts where a polysilicon (p-Si) layer and a single crystal Si layer are exposed, when a semiconductor element is formed on an Si substrate. CONSTITUTION: In a process wherein oxide films are formed in the parts where a p-Si layer 1 and a single crystal Si layer 7 are exposed, a nitriding process for nitriding only the p-Si layer 1 just before oxidizing is performed is executed, and an oxide film forming process is subsequently executed. In the nitriding process, an Si substrate is exposed to a nitrogen (N2 ) atmosphere at a specific temperature for a specific period. The nitriding rate is different between the p-Si film 1 and the Si layer 7, and only the p-Si layer 1 is nitrided. The thickness of the nitride film of the p-Si layer 1 is controlled by adjusting the exposure time. In the subsequent process for forming oxide films, the oxide film formation rate of the p-Si layer 1 decreases, so that the oxide film can be thinned. Thereby the thickness of an oxide film 3 of the p-Si layer 1 can be controlled.

9. 发明专利

JPH03263367A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03263367A
公开(公告)日：1991-11-22
申请号：JP32821390
申请日：1990-11-27
申请人： NIPPON DENSO CO
发明人： ISOBE YOSHIHIKO , IIDA MAKIO
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06
摘要： PURPOSE:To make a resistance-temperature characteristic close to '0' by a method wherein a polycrystalline silicon resistor which contains impurities of a negative resistance-temperature characteristic and impurities of a positive resistance-temperature characteristic is formed in a high-concentration region of impurities of a silicon resistor. CONSTITUTION:Impurities (arsenic) whose resistance-temperature characteristic is negative are added to polycrystalline silicon, by an ion-implantation method, in a high-concentration region as a range where the concentration of impurities of a polycrystalline silicon resistor 5 can be trimmed. At the same time, impurities (phosphorus) whose resistance-temperature characteristic is positive are added to polycrystalline silicon, by using a thermal diffusion method, in the high-concentration region as the range where the concentration of the impurities of the polycrystalline silicon resistor 5 can be trimmed. An electric current is applied to the polycrystalline silicon resistor 5 at a current density of a threshold value or higher, and its resistance value is adjusted. As a result, a high-accuracy IC provided with the polycrystalline silicon resistor, for trimming use, containing the impurities whose total sum of impurity concentrations is about 10 cm or higher can be manufactured. At the polycrystalline silicon resistor, a resistance-temperature characteristic can be made appoximate to '0'.

10. 发明专利

JP2536303B2 失效
公开(公告)号：JP2536303B2
公开(公告)日：1996-09-18
申请号：JP20082790
申请日：1990-07-27
申请人： NIPPON DENSO CO
发明人： KAMYA TETSUAKI , KUMAZAWA TAKAHIRO , ISOBE YOSHIHIKO , IIDA MAKIO
IPC分类号： H01L27/04 , H01L21/316 , H01L21/822

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